Multi-Stage Driving Circuit for Stable Display Gate Signals
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Solution Overview
Problem
Existing display devices face challenges in stably outputting gate signals with a small size, requiring improved driving circuits that can efficiently manage multiple stages and reduce transistor stress and leakage currents.
Innovation Solution
A driving circuit with a plurality of stages, each comprising specific transistors and capacitors, that alternately input clock signals with phase shifts to stabilize node voltages and minimize voltage differences, thereby reducing transistor stress and leakage currents.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional driving circuit is used, then the circuit can output gate signals, but the transistor stress and leakage currents increase, reducing stability
Solution Approach 1:
The driving circuit is divided into multiple stages, where each stage includes specific transistors (first transistor T1, second transistor T2, third transistor T3, fourth transistor T4, fifth transistor T5) and capacitors (first capacitor C1, second capacitor C2, third capacitor C3) that work together to segment the signal processing function. This segmentation allows each transistor to operate under optimized conditions, reducing individual transistor stress and leakage currents while maintaining stable gate signal output across the entire circuit.
2Area of stationary object
If the circuit size is reduced, then the display device becomes more compact, but the stability of gate signal output deteriorates
Solution Approach 1:
The circuit merges multiple functions into a compact stage structure where transistors and capacitors are integrated to perform signal amplification, voltage stabilization, and clock signal processing simultaneously. The first capacitor C1 is connected between the first node and ground, the second capacitor C2 between the second node and ground, and the third capacitor C3 between the output terminal and ground, creating a compact yet stable configuration that maintains reliability while reducing overall circuit area.
Solution Approach 2:
The circuit employs periodic clock signals (first clock signal CLK1 and second clock signal CLK2) that alternately control the switching of transistors T1-T5. This periodic action allows the circuit to process gate signals in discrete cycles, enabling stable output even in a compact design by resetting and refreshing signal levels at regular intervals, preventing signal degradation that would otherwise require larger circuit dimensions.
3Reliability
If multiple stages are added to improve signal stability, then the gate signal output becomes more stable, but the device complexity increases
Solution Approach 1:
Each stage in the multi-stage driving circuit is designed as a universal module that can handle multiple functions: signal amplification through transistors T1-T3, voltage stabilization through capacitors C1-C3, and clock signal synchronization. This multi-functionality allows the same stage design to be replicated across multiple stages without proportionally increasing complexity, as each stage uses the same set of components performing integrated functions rather than requiring separate dedicated components for each function.
Data Source
AI summary
A driving circuit includes stages. Each of stages includes a first transistor connected between a first node and a first terminal, and including a gate connected to a first clock terminal to which a first clock signal is input, a second transistor connected between the first and second nodes and including a gate connected to the first clock terminal, a third transistor connected between the first node and a second clock terminal to which a second clock signal is input, and including a gate connected to the first node, a first capacitor connected between the third transistor and the first node, a fourth transistor connected between output and second terminals to which a first voltage is applied, and including a gate connected to the first clock terminal, and a fifth transistor connected between the output terminal and the second clock terminal and including a gate connected to the second node.