Multi-Stage FPGA Routing to Reduce TDM Signal Delay
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Solution Overview
Problem
The challenge of optimizing time division multiplexing in multi-FPGA prototyping systems to reduce inter-chip signal delay and improve routability, given the limitations of existing FPGA verification methods such as software simulation and hardware emulation, which are time-consuming and costly, especially with increasing chip scales.
Innovation Solution
A multi-stage FPGA routing method that involves collecting sets of FPGAs, connection pairs, and nets, assigning TRs based on net delays, and iteratively optimizing net groups through TR reduction and edge validation to minimize maximum system clock period delay.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If time division multiplexing is used to transmit multiple inter-chip signals simultaneously within one system clock period, then the routability of the entire system is improved, but the delay of the inter-chip signals is increased
Solution Approach 1:
The patent segments the time division multiplexing process into multiple stages. Instead of assigning all signals to a single multiplexing stage, the routing method divides signals into different stages based on their delay requirements and net group classifications. This segmentation allows signals to be transmitted in multiple time slots across different stages, reducing the multiplexing ratio in each stage and thereby minimizing signal delay while maintaining system routability.
Solution Approach 2:
The patent implements dynamic TR (time ratio) assignment where the multiplexing ratio is not fixed but adjusted based on the specific requirements of different net groups. The system dynamically determines the TR value for each stage based on the number of signals and their delay characteristics, allowing optimal resource utilization and minimizing overall delay while ensuring all signals can be routed successfully.
2Adaptability or versatility
If multiple FPGAs are connected to form a multi-FPGA prototyping system, then the scalability of the system is improved, but the complexity of routing and timing optimization increases
Solution Approach 1:
The patent segments the routing problem into manageable parts by dividing signals into different net groups based on their delay requirements and routing characteristics. Each net group is processed independently through dedicated routing stages, which simplifies the overall routing complexity even as the system scales to multiple FPGAs. This segmentation allows the complexity to be distributed across multiple manageable tasks rather than handled as a single complex problem.
Solution Approach 2:
The patent performs preliminary actions by pre-classifying signals into different net groups before the actual routing process. This preliminary classification based on delay requirements and signal characteristics allows the routing algorithm to prepare and optimize paths in advance, reducing the computational complexity during routing and making the system more scalable to multiple FPGAs.
3Adaptability or versatility
If the number of FPGA pins is greater than that of FPGA inter-chip signals, then the connectivity of the system is improved, but the efficiency of time division multiplexing decreases
Solution Approach 1:
The patent implements dynamic TR assignment where the multiplexing ratio is adjusted based on the actual number of signals and their delay requirements. When the number of pins exceeds the number of inter-chip signals, the system dynamically reduces the TR value to optimize multiplexing efficiency. This dynamic adjustment ensures that resources are not wasted on excessive multiplexing while maintaining sufficient connectivity, thereby improving productivity without sacrificing connectivity.
Solution Approach 2:
The patent changes the TR parameter dynamically based on system conditions. When there are more pins than signals, the system adjusts the TR value to reflect the actual multiplexing needs, preventing inefficient over-multiplexing. This parameter change allows the system to maintain good connectivity while improving multiplexing efficiency by aligning the TR value with the actual signal transmission requirements.
Data Source
AI summary
A multi-stage FPGA routing method for optimizing time division multiplexing comprises the following steps: S1: collecting an FPGA set, an FPGA connection pair set, a net set and a net group set; S2: acquiring a routing topology of each net according to the FPGA set, the FPGA connection pair set, the net set and the net group set under the condition where TRs are not assigned; S3: assigning a corresponding TR to each edge of each net according to different delay of each net group; and S4: performing TR reduction and edge validation cyclically, iteratively optimizing net groups with TR being greater than a preset value until iteration end conditions are met, so as to obtain an optimal routing result. The multi-stage FPGA routing method may optimize the delay of inter-chip signals of a multi-FPGA prototype system and guarantee the routability of the multi-FPGA prototype system.