Multi-Stage Gate Driving Circuit with Phase-Shifted Clocks for Stable Output
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Solution Overview
Problem
Existing display apparatuses face challenges in efficiently and stably outputting gate signals due to the complexity and size of their gate driving circuits, which can lead to instability and inefficiencies.
Innovation Solution
A small-sized gate driving circuit is designed with a specific configuration of transistors and capacitors, including P-type and N-type transistors, and a phase-shifted clock signal system to stabilize gate signal output, utilizing a pull-up and pull-down transistor structure to manage voltage levels effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional gate driving circuit is used, then gate signals can be output, but the circuit size is large and stability is poor
Solution Approach 1:
The gate driving circuit is divided into multiple stages, with each stage independently generating gate signals for specific gate lines. This segmentation allows for reduced complexity in each individual stage while maintaining overall functionality, directly addressing the contradiction between circuit size and stability.
Solution Approach 2:
Different transistor types (P-type and N-type) are strategically assigned to different positions within the circuit to optimize local performance. The pull-up transistor uses P-type while the pull-down transistor uses N-type, creating local quality variations that improve overall circuit stability without requiring a large circuit size.
2Reliability
If transistor stress is not managed, then circuit operation is simple, but transistor degradation occurs and reliability decreases
Solution Approach 1:
The circuit dynamically changes voltage parameters during operation. The pull-up transistor raises the output node voltage to a first voltage level while the pull-down transistor lowers it to a second voltage level. This parameter changing approach manages transistor stress by controlling voltage transitions, improving reliability without excessive structural complexity.
Solution Approach 2:
The gate driving circuit operates through periodic clock signals that alternately activate the pull-up and pull-down transistors. This periodic action allows transistors to rest during non-active periods, reducing cumulative stress and degradation while maintaining a relatively simple circuit structure.
Data Source
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AI summary
A driving circuit including a plurality of stages to output gate signals to pixels, each of the stages includes: a first transistor (T11) between a first terminal (IN) and a first node (A1) and including a gate connected to a first clock terminal (CK1), wherein a start signal is input to the first terminal and a first clock signal (CLK1) is input to the first clock terminal; a second transistor (T12) between the first node and a second node (Q1) and including a gate connected to the first clock terminal; a third transistor (T13) between a second clock terminal (CK2) and the first node, wherein a second clock signal (CLK2) is input to the second clock terminal; a pull-up transistor (T15) between a second terminal (V1) and an output terminal (OUT); and a pull-down (T16) transistor between the output terminal and the second clock terminal.