Multi-Stage Hierarchical Network Routing with Hop Wires
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Solution Overview
Problem
Current multi-stage hierarchical networks in semiconductor chips face challenges with high silicon area consumption, long signal propagation delays, and high power usage due to full crossbars or sparse crossbars in island-style architectures, which hinder efficient routing and performance.
Innovation Solution
Optimized multi-stage hierarchical networks using horizontal and vertical wires in a two-dimensional grid arrangement, with hop wires or multi-drop hop wires connecting switches across rings, exploiting spatial locality to reduce crosspoints, signal latency, and power consumption, while enabling fast scheduling and routing methods for broadcast, unicast, and multicast connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If full crossbars or sparse crossbars are used in island-style architectures, then routing capability is improved, but silicon area consumption increases
Solution Approach 1:
The network is divided into multiple stages with smaller switching blocks rather than using a single large crossbar. Each stage processes a subset of connections, reducing the size of individual switching blocks and overall silicon area while maintaining full routing capability through the multi-stage architecture.
Solution Approach 2:
The patent transitions from a two-dimensional crossbar architecture to a multi-stage three-dimensional network structure. Connections are established through multiple stages rather than direct point-to-point links, reducing area by distributing switching functions across stages while preserving routing flexibility.
2Adaptability or versatility
If full crossbars or sparse crossbars are used in island-style architectures, then routing capability is improved, but signal propagation delay increases
Solution Approach 1:
The signal path is divided into multiple stages with shorter inter-stage connections. Rather than long direct paths through large crossbars, signals traverse multiple shorter segments through smaller switching blocks, reducing propagation delay while maintaining routing capability.
Solution Approach 2:
The network adds a temporal dimension through multiple stages, allowing signals to progress through sequential stages rather than requiring long simultaneous paths. This multi-stage approach reduces signal propagation delay by breaking down long paths into shorter segments.
3Adaptability or versatility
If full crossbars or sparse crossbars are used in island-style architectures, then routing capability is improved, but power usage increases
Solution Approach 1:
Power consumption is distributed across multiple stages with smaller switching blocks. Each stage processes only a subset of connections, reducing the power required per stage and overall power consumption while maintaining full routing capability through the cascaded architecture.
Solution Approach 2:
The network distributes power consumption across multiple temporal and spatial stages rather than concentrating it in a single large crossbar. This multi-stage approach reduces peak power usage and overall energy consumption by processing connections sequentially through stages.
4Area of stationary object
If hop wires or multi-drop hop wires are used to connect switches across rings, then area is reduced, but wire complexity increases
Solution Approach 1:
Hop wires and multi-drop wires serve multiple functions: they connect switches across rings, provide broadcast capabilities, and enable both unicast and multicast connections. This multi-functionality reduces the need for separate dedicated connections, simplifying the overall wire structure while reducing area.
Solution Approach 2:
Multiple point-to-point connections are merged into shared hop wires and multi-drop wires. Instead of having separate wires for each connection, the network uses shared wires that can carry multiple connections through proper switching, reducing wire count and area while managing complexity through controlled sharing.
Data Source
AI summary
Significantly optimized multi-stage networks including scheduling methods for faster scheduling of connections, useful in wide target applications, with VLSI layouts using only horizontal wires and vertical wires to route large scale partial multi-stage hierarchical networks having inlet and outlet links, and laid out in an integrated circuit device in a two-dimensional grid arrangement of blocks are disclosed. The optimized multi-stage networks in each block employ one or more slices of rings of stages of switches with inlet and outlet links of partial multi-stage hierarchical networks connecting to rings from either left-hand side or right-hand side; and employ hop wires or multi-drop hop wires wherein hop wires or multi-drop wires are connected from switches of stages of rings of slices of a first partial multi-stage hierarchical network switches of stages of a rings of slices of the first or a second partial multi-stage hierarchical network.