Multi-Stage Logic Regions for High-Input FPGA Functions
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Solution Overview
Problem
Programmable integrated circuits face inefficiencies in resource utilization when configuring custom logic functions, as they often require more inputs than available in individual programmable logic circuits, leading to underutilization of circuitry and increased silicon area requirements.
Innovation Solution
The implementation of programmable logic regions with cascaded processing stages and multiplexer circuitry allows for efficient use of resources by sharing inputs between look-up tables and configuring them in cascade or independent modes, enabling the performance of custom logic functions with more inputs without routing through interconnects, thus optimizing circuitry usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a custom logic function requiring more inputs than available in a single programmable logic circuit is implemented, then the logic function can be performed, but resource utilization becomes inefficient and silicon area increases
Solution Approach 1:
The patent divides the programmable logic region into multiple logic circuits, each capable of implementing a portion of the custom logic function. These segmented logic circuits are then interconnected through local interconnects to collectively perform the complete multi-input logic function, thereby improving resource utilization while maintaining adaptability
Solution Approach 2:
The patent combines multiple logic circuits and their interconnect resources to implement a single custom logic function. By merging the capabilities of multiple logic circuits and sharing interconnect resources among them, the system achieves efficient resource utilization while maintaining the ability to implement complex multi-input logic functions
2Adaptability or versatility
If additional interconnect resources are provided to route more inputs to programmable logic circuits, then custom logic functions with more inputs can be implemented, but silicon area and device complexity increase
Solution Approach 1:
The patent makes interconnect resources universal by enabling them to serve multiple logic circuits simultaneously. The same interconnect resources can be dynamically allocated to different logic circuits depending on the configuration, allowing the system to implement custom logic functions with more inputs without proportionally increasing silicon area
Solution Approach 2:
The patent segments the logic function implementation across multiple logic circuits that share common interconnect resources. This segmentation allows the interconnect structure to serve multiple purposes and support more inputs without requiring a proportional increase in interconnect quantity, thereby reducing silicon area usage
3Ease of manufacture
If underutilized programmable logic circuits are used to implement custom logic functions, then implementation is simplified, but resource utilization efficiency decreases
Solution Approach 1:
The patent introduces dynamic configurability that allows the system to adaptively allocate logic circuits and interconnect resources based on the specific requirements of each custom logic function. This dynamic approach enables efficient resource utilization while maintaining ease of implementation through programmable control
Solution Approach 2:
The patent employs configuration mechanisms that allow the system to optimize resource allocation based on the specific logic function being implemented. The programmable interconnects and logic circuits can be configured to match the actual resource requirements, preventing both underutilization and over-provisioning
Data Source
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AI summary
A programmable logic region (28) on a programmable integrated circuit may include a first set (34) of look-up tables (A, C) that receive programmable logic region input signals and a second set (38) of look-up tables (B, D) that produce programmable logic region output signals. Multiplexer circuitry (40) may be interposed between the first (34) and second sets (38) of look-up tables (A, B, C, D). The multiplexer circuitry (36) may receive the programmable logic region input signals in parallel with the output signals from the first set of look-up tables (A, C) and may provide corresponding selected signals to the second set of look-up tables (B, D). The programmable logic region input signals may be shared by the first and second sets of look-up tables. Logic circuitry may be coupled to outputs of the first and second sets of look-up tables. The logic circuitry may be configured to logically combine output signals from the first and second sets of look-up tables.