Multi-Stage Memory Data-Path Partitioning for Lower RC Delay
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Solution Overview
Problem
Existing memory architectures face challenges in reducing memory access time and power consumption due to increased capacitance and resistance, leading to longer access times and higher power consumption, particularly in lower technology nodes.
Innovation Solution
Implementing a multi-stage data path-partitioning circuit with strategic placement of write assist circuits and charge pumps, reducing global bit-line lengths and capacitance, and optimizing RC delay through partitioning into three levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If buffers are inserted into clock paths to optimize and reduce resistance-capacitance delay, then memory access time is improved, but silicon area and gate delay increase
Solution Approach 1:
The patent divides the memory array into multiple banks (e.g., first bank, second bank, third bank, fourth bank) with separate clock paths. Each bank receives clock signals through dedicated buffers, allowing localized optimization without requiring buffers across the entire memory array. This segmentation reduces the total number of buffers needed while maintaining improved access time in each bank.
2Speed
If buffers are inserted into clock paths to optimize resistance-capacitance delay, then memory access time is improved, but gate delay increases
Solution Approach 1:
The patent implements different clock path configurations for different banks based on their specific requirements. Not all banks require the same buffering strategy - some banks may need full buffering while others can use reduced buffering or alternative clock distribution methods. This local optimization allows each bank to achieve minimal gate delay while maintaining improved access time.
3Speed
If more input gate capacitance and metal capacitance are introduced through buffers, then resistance-capacitance delay is reduced, but toggle power increases
Solution Approach 1:
By dividing the memory into multiple banks with separate clock paths, the patent reduces the total capacitance that each buffer must drive. Instead of one large buffer driving the entire memory array, multiple smaller buffers each drive a portion of the array, reducing the capacitance load per buffer and thereby reducing toggle power consumption.
4Loss of energy
If global bit-line lengths are reduced through partitioning, then capacitance decreases, but device complexity increases
Solution Approach 1:
The patent partitions the memory array into multiple banks, each with its own local bit-lines and sense amplifiers. This segmentation reduces the length of global bit-lines, thereby reducing capacitance and power consumption. The complexity increase is managed through modular design, where each bank follows a standardized structure that can be replicated.
Solution Approach 2:
The patent introduces a bank-level dimension to the memory architecture, organizing memory cells into hierarchical groups (banks within arrays). This dimensional organization allows bit-lines to be localized within banks rather than spanning the entire array, reducing capacitance while the hierarchical structure manages the added complexity.
Data Source
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AI summary
A memory (300) comprising a multi stage data path-partitioning circuit, the memory (300, 400) comprising at least:a first data path level partitioning (310) comprising at least one input configured to input data to or output data from the memory (300, 400) via at least one global input-output circuit (360, 362); a second data path level partitioning (320) configured to input data to or output data from the memory (300, 400) between one of a plurality of write assist circuits (430, 431, 432, 433) and one of the at least one global input-output circuit (360, 362) wherein at least one of the plurality of write assist circuits (430, 431, 432, 433) and at least another of the plurality of write assist circuits (430, 431, 432, 433) are located in a central portion of an upper bitcell memory array (411, 412, 413, 414, 421, 422, 423, 424) and an lower bitcell memory array (415, 416, 417, 418, 425, 426, 427, 428) respectively; a third data path level partitioning (330) configured to input data to or output data from the memory (300, 400) between one of a plurality of column multiplexing circuitry and sense amplifier circuits (441, 442, 443, 444, 445, 446, 447, 448) and one of the plurality of write assist circuits (430, 431, 432, 433).