Multi-Stage Memory Programming With Three-State Parity Reconstruction
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Solution Overview
Problem
Existing non-volatile memory programming techniques require maintaining user data in the memory device between foggy and fine passes, leading to resource inefficiency due to low reliability after the foggy pass.
Innovation Solution
A multi-pass programming technique where memory cells are initially programmed to foggy data and parity data with three possible states, allowing for reconstruction of final data before the second pass, reducing the need to maintain the final data between passes and improving reliability with minimal performance loss.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If user data is maintained in the memory device between foggy and fine passes, then data reliability is improved, but resource utilization deteriorates
Solution Approach 1:
The patent extracts the user data from the memory device after the foggy pass, storing it externally instead of maintaining it within the memory device. This allows the memory resources to be freed for other operations while the data is reconstructed and programmed in the fine pass, thus improving resource utilization without compromising data reliability.
Solution Approach 2:
The patent performs preliminary programming of foggy data in the first pass, which prepares the data in advance for the fine pass. This preliminary action allows the data to be reconstructed from foggy data and parity data before the fine programming pass, eliminating the need to maintain the complete user data in the memory device between passes.
2Productivity
If programming is performed in a single pass, then programming speed is improved, but programming reliability deteriorates
Solution Approach 1:
The patent segments the programming operation into two distinct passes: a foggy pass that programs data at high speed with relaxed verification, and a fine pass that programs the same data with strict verification. This segmentation allows the system to achieve both high programming speed in the first pass and high programming reliability in the second pass, resolving the contradiction between speed and reliability.
Data Source
AI summary
The memory device includes a memory block with an array of memory cells arranged word lines. The memory device also includes control circuitry that is configured to program final data into a selected word line in a multi-pass programming operation that includes a first pass and a second pass. In the first pass, the control circuitry is configured to program the memory cells of the selected word line to foggy data and program parity data in the memory device. The parity data includes three possible data states. Prior to the second pass, the control circuitry is configured to read the foggy data and the parity data and reconstruct the final data from the foggy data and the parity data. In the second pass, the control circuitry is configured to program the memory cells of the selected word line from the foggy data to the final data.