Multi-Stage Memory Sensing to Reduce Noise and Signal Settling Time
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Solution Overview
Problem
Ferroelectric memory devices face challenges in accurate read operations due to noise susceptibility and prolonged signal development times when transistors operate in the deep sub-threshold regime, affecting the reliability and speed of memory cell sensing.
Innovation Solution
Implementing a multi-stage sensing approach where the transistor is toggled from active to inactive and back to active during the read operation, reducing the time spent in the deep sub-threshold regime and allowing for faster signal development and latching.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by stationary object
If the transistor operates in the deep sub-threshold regime to enable low-power read operations, then power consumption is reduced, but noise susceptibility increases and signal development time is prolonged
Solution Approach 1:
The read operation is divided into multiple stages with distinct transistor operating modes. In the first stage, the transistor operates in the deep sub-threshold regime for low-power charge transfer. In the second stage, the transistor transitions to a higher conduction state for rapid signal development and sense amplifier activation. This segmentation allows the system to benefit from both low-power operation and high-speed signal development without compromise.
2Use of energy by stationary object
If the transistor operates in the deep sub-threshold regime, then power consumption is reduced, but the time required for signal settling is prolonged
Solution Approach 1:
The read operation employs periodic action through multi-stage timing sequences. The transistor operates in different conduction states during different time periods: initially in deep sub-threshold mode for charge transfer, then transitioning to a higher conduction state for rapid signal development. This time-varying operation allows the system to achieve both low power consumption during the critical charge transfer phase and fast signal settling during the readout phase.
3Speed
If the transistor remains active throughout the read operation, then signal development is continuous, but noise is introduced and additional operations cannot be performed
Solution Approach 1:
The harmful noise-generating activity of the transistor is extracted and limited to specific time periods. The transistor is deactivated during portions of the read operation when its activity would introduce noise, while remaining active during critical phases where signal development is needed. This selective activation removes the harmful noise-introducing aspect while preserving the beneficial signal development function.
Data Source
AI summary
Methods and devices for reading a memory cell using multi-stage memory sensing are described. The memory cell may be coupled to a digit line after the digit line during a read operation. A transistor may be activated to couple an amplifier capacitor with the digit line during the read operation. The transistor may be deactivated for a portion of the read operation to isolate the amplifier capacitor from the digit line while the memory cell is coupled to the digit line. The transistor may be reactivated to recouple the amplifier capacitor to the digit line to help determine the value of the memory cell.