Multi-Stage Pyramid Network Fabric for FPGA Routing
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Solution Overview
Problem
Existing VLSI layouts of multi-stage interconnection networks such as Benes, Benes Pyramid, Butterfly fat tree networks in integrated circuits are inefficient, not scalable, and impractical due to large area requirements, high power consumption, and increased latency, making them unsuitable for practical routing applications in FPGAs and parallel computing.
Innovation Solution
The development of optimized multi-stage pyramid networks with VLSI layouts that utilize horizontal and vertical links in a two-dimensional grid arrangement, featuring slices of rings of switches with varying multiplexer sizes, allowing for automatic generation of fabrics with improved routability, reduced crosspoints, and faster scheduling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If traditional multi-stage interconnection networks (Benes, Butterfly fat tree) are used in VLSI layouts, then connectivity is achieved, but area requirements increase significantly
Solution Approach 1:
The network is divided into multiple stages with each stage containing a specific number of switches. The patent uses a multi-stage architecture where the first stage has a different number of switches than subsequent stages, allowing for optimized area utilization while maintaining full connectivity. This segmentation enables the network to achieve the same connectivity function with reduced total area compared to traditional uniform multi-stage networks.
Solution Approach 2:
The patent applies different switch configurations to different stages of the network. The first stage uses a specific number of switches optimized for input connectivity, while the second and third stages use different switch counts optimized for intermediate routing and output connectivity respectively. This local optimization of switch distribution across stages reduces the overall area requirement while maintaining full adaptability.
2Adaptability or versatility
If traditional multi-stage networks are implemented, then routing capability is provided, but power consumption increases
Solution Approach 1:
The patent extracts and eliminates redundant switching elements from the traditional multi-stage network architecture. By carefully calculating the minimum number of switches required in each stage to achieve full routing capability, the design removes unnecessary switches that would contribute to power consumption without providing additional routing functionality. This extraction principle reduces power consumption while preserving complete routing capability.
Solution Approach 2:
The patent changes the parameter of switch count in each stage from the traditional uniform configuration to a non-uniform configuration. The first stage has a different number of switches compared to the second and third stages, optimized for the specific routing requirements at each level. This parameter optimization reduces the total number of active switching elements, thereby reducing overall power consumption while maintaining full routing capability.
3Device complexity
If traditional VLSI layouts are used, then network structure is realized, but signal latency increases
Solution Approach 1:
The patent arranges the network stages and switches in a predetermined optimized configuration before operation. The first stage switches are positioned to handle initial routing decisions, followed by second and third stages that continue the routing path with minimal detours. This preliminary structural arrangement ensures that signals traverse the network in an optimized path, reducing latency while maintaining the required network structure complexity.
Solution Approach 2:
The patent transitions from a traditional two-dimensional grid layout to a three-dimensional stacked architecture. Multiple stages of switches are arranged in vertical layers with optimized inter-layer connections. This dimensional change allows signals to progress through the network stages more directly, reducing the number of routing hops and associated latency while maintaining the necessary network structure.
4Adaptability or versatility
If scalable network designs are implemented, then adaptability to different sizes is achieved, but implementation practicality decreases
Solution Approach 1:
The patent designs a universal multi-stage network architecture that can be configured for different network sizes by adjusting the number of switches in each stage. The same basic three-stage structure serves multiple functions: it provides full connectivity, supports various network dimensions, and maintains optimized routing paths. This universal design allows the network to scale while remaining practical to implement, as the fundamental architecture remains consistent across different configurations.
Solution Approach 2:
The patent enables scalability through parameter adjustment rather than structural redesign. The number of switches in each stage can be modified to accommodate different network sizes and requirements, while the overall three-stage architecture remains unchanged. This parameter-based scalability makes the design practical to implement, as it allows customization for different applications without requiring complete redesign, thus balancing adaptability with manufacturing ease.
Data Source
AI summary
Systems and methods to automatically or manually generate various multi-stage pyramid network based fabrics, either partially connected or fully connected, are disclosed by changing different parameters of multi-stage pyramid network including such as number of slices, number of rings, number of stages, number of switches, number of multiplexers, the size of the multiplexers in any switch, connections between stages of rings either between the same numbered stages (same level stages) or different numbered stages, single or multi-drop hop wires, hop wires of different hop lengths, hop wires outgoing to different directions, hop wires incoming from different directions, number of hop wires based on the number and type of inlet and outlet links of large scale sub-integrated circuit blocks. One or more parameters are changed in each iteration so that optimized fabrics are generated, at the end of iterations, to route a given set of benchmarks or designs having a specific connection requirements.