Multi-Stage Scheduler for Processor and Bandwidth Allocation
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Solution Overview
Problem
Conventional scheduling algorithms fail to effectively manage processor resource bottlenecks in telecommunications applications, leading to underutilization of output bandwidth, especially in processor-intensive traffic scenarios where the processing power is limited and fairness criteria are difficult to determine accurately.
Innovation Solution
A multi-stage scheduling technique that separates incoming traffic into multiple flows and schedules access to both processor and output bandwidth resources using a weighted Deficit Round-Robin (DRR) algorithm, with adjustable weights based on queue length to ensure fair allocation and prevent processor-intensive traffic from overwhelming the processor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If conventional scheduling algorithms are used to manage processor resource bottlenecks, then processor resource allocation is simplified, but output bandwidth utilization deteriorates due to underutilization
Solution Approach 1:
The patent divides the scheduling process into two distinct stages: a first stage that schedules access to processor resources for multiple traffic flows, and a second stage that schedules access to output bandwidth resources. This segmentation allows each stage to optimize for its specific resource type, preventing processor-intensive traffic from overwhelming the processor while ensuring fair allocation and improving overall output bandwidth utilization.
2Productivity
If processor resource allocation is prioritized, then processor bottleneck is reduced, but output bandwidth resource allocation fairness deteriorates
Solution Approach 1:
By separating scheduling into two independent stages, the patent ensures that processor resource allocation does not compromise output bandwidth fairness. The first stage handles processor resource allocation based on traffic flow characteristics, while the second stage independently handles output bandwidth allocation based on queue lengths and weights, maintaining fairness for all traffic flows.
Solution Approach 2:
The patent implements feedback mechanisms in both scheduling stages. The second stage uses feedback from queue length measurements to dynamically adjust scheduling decisions for output bandwidth allocation. The first stage also incorporates feedback to adapt processor resource allocation based on actual traffic conditions, ensuring both efficiency and fairness.
3Loss of time
If simple scheduling algorithms are used, then hardware processing time is reduced, but allocation fairness deteriorates
Solution Approach 1:
The patent segments the scheduling algorithm into two stages, each performing a specific function. The first stage quickly schedules processor access using lightweight criteria, while the second stage ensures fair bandwidth allocation using queue length feedback and weight-based scheduling. This segmentation allows simple, fast decisions in the first stage while maintaining fairness in the second stage.
Solution Approach 2:
The patent incorporates feedback mechanisms that enable fair allocation without complex processing. The second stage uses feedback from queue length measurements to dynamically adjust scheduling weights, ensuring fair bandwidth distribution. This feedback approach maintains allocation fairness while keeping the overall processing time low through efficient feedback-driven decisions.
Data Source
AI summary
A multi-stage scheduler that provides improved bandwidth utilization in the presence of processor intensive traffic is disclosed. Incoming traffic is separated into multiple traffic flows. Data blocks of the traffic flows are scheduled for access to a processor resource using a first scheduling algorithm, and processed by the processor resource as scheduled by the first scheduling algorithm. The processed data blocks of the traffic flows are scheduled for access to a bandwidth resource using a second scheduling algorithm, and provided to the bandwidth resource as scheduled by the second scheduling algorithm. The multi-stage scheduler in an illustrative embodiment may be implemented in a network processor integrated circuit or other processing device of a communication system.