Multi-Stage TSV via design for 3D integration
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Solution Overview
Problem
Current through-substrate vias (TSVs) in 3D semiconductor stacking face challenges such as large cross-sectional area requirements for high aspect ratios, leading to integration and reliability issues like CTE mismatch and wafer bowing, while maintaining conductivity and minimizing area consumption.
Innovation Solution
A multi-stage TSV process is developed, where a top section with a current minimum cross-sectional area is formed first, filled with sacrificial material, and then joined with a bottom section of larger cross-sectional area after substrate thinning, allowing for a continuous conductive path without initial conductive filling, which addresses thermal expansion differences and reduces wafer bowing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If a TSV is formed with high aspect ratio to minimize area consumption, then area efficiency is improved, but manufacturing difficulty increases due to process limitations
Solution Approach 1:
The TSV formation process is segmented into multiple stages: first forming a shallow via with moderate aspect ratio, filling it with sacrificial material, then forming a deeper via to connect to lower interconnect layers. This segmentation allows each via section to have manageable dimensions that are easier to manufacture while achieving the overall high aspect ratio needed for area efficiency.
Solution Approach 2:
The patent transitions from a single-vertical-dimension via structure to a multi-stage via structure that incorporates both vertical depth and lateral positioning dimensions. By forming vias at different depths and connecting them through sacrificial material removal, the solution achieves high aspect ratio connectivity while maintaining manufacturability through controlled dimensional transitions.
2Reliability
If copper is used for TSV to achieve high conductivity, then electrical conductivity is improved, but reliability deteriorates due to CTE mismatch and wafer bowing
Solution Approach 1:
The patent extracts the problematic copper material from the TSV structure and replaces it with tungsten, which has lower conductivity per unit area but eliminates the CTE mismatch and wafer bowing issues. The multi-stage via design compensates for the lower conductivity by providing optimized conductive pathways that achieve sufficient electrical performance without the harmful thermal expansion effects of copper.
3Ease of manufacture
If TSV cross-sectional area is increased to maintain moderate aspect ratio, then manufacturing ease is improved, but area consumption increases reducing circuit density
Solution Approach 1:
The via structure is segmented into multiple sections with different cross-sectional areas optimized for their respective functions. The upper via section has smaller cross-section for area efficiency, while the lower via section provides the necessary conductive area for current carrying capacity. This segmentation allows the overall structure to achieve high area efficiency while maintaining manufacturability through appropriate dimensional transitions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach minimizes the area consumed by TSVs, maintains conductivity, and avoids integration and reliability challenges by allowing for a manageable aspect ratio and reduced wafer bowing, enhancing the density and performance of integrated circuits.
Implementation Method 1
The fill material can be selected to limit thermal expansion differences relative to the substrate
Implementation Method 2
The conductive path of the TSV can be formed as a single deposition of material extending continuously from the top substrate surface to the bottom substrate surface
Data Source
AI summary
A TSV can be formed having a top section via formed through the top substrate surface and a bottom section via formed through the bottom substrate surface. The top section cross section can have a minimum cross section corresponding to design rules, and the top section depth can correspond to a workable aspect ratio. The top section via can be filled or plugged so that top side processing can be continued. The bottom section via can have a larger cross section for ease of forming a conductive path therethrough. The bottom section via extends from the back side to the bottom of the top section via and is formed after the substrate has been thinned. The TSV is can be completed by forming a conductive path after removing sacrificial fill materials from the joined top and bottom section vias.