Multi-Staged Pipelined GNSS Receiver Architecture for FPGA Scaling
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Solution Overview
Problem
Existing GNSS receivers face challenges in efficiently processing multiple satellite signals and achieving high accuracy due to limitations in processing power and silicon die area, particularly with FPGA implementations.
Innovation Solution
A multi-staged pipelined architecture for GNSS receivers is introduced, utilizing pipelines with identical digital logic circuits separated by latches, allowing for faster state updates and increased processing efficiency by reusing logic circuits multiple times through overclocking, effectively increasing the equivalent number of baseband channels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If traditional single-stage processing architecture is used, then device complexity is low, but processing power and accuracy are insufficient
Solution Approach 1:
The patent divides the signal processing function into multiple identical processing stages arranged in parallel. Each stage processes a portion of the satellite signal independently through the same digital logic circuits, allowing the system to handle multiple signals simultaneously. This segmentation increases processing power while maintaining manageable complexity through modular repetition of identical units.
Solution Approach 2:
The patent transitions from single-stage sequential processing to multi-stage parallel processing by adding a temporal/dimensional dimension. Multiple stages process signals at different times or in different parallel channels, effectively increasing the processing capacity without proportionally increasing the complexity of individual stages.
2Productivity
If more processing stages are added to handle multiple satellite signals, then processing power increases, but silicon die area increases
Solution Approach 1:
The patent employs identical digital logic circuits in multiple processing stages, where each stage can perform the same set of operations. This universality allows the system to process multiple satellite signals simultaneously using the same hardware resources repeated in different stages, increasing processing efficiency while controlling silicon die area through efficient resource reuse.
Solution Approach 2:
The patent combines multiple processing functions into integrated pipelines where digital logic circuits, latches, and signal processing operations are merged into unified processing stages. This merging reduces the overall silicon die area by eliminating redundant components while maintaining the ability to handle multiple satellite signals through pipelined architecture.
3Speed
If pipelined architecture with multiple stages is used, then processing speed increases, but device complexity increases
Solution Approach 1:
The patent incorporates latches between processing stages that store intermediate results and prepare data for the next stage. This preliminary action allows each stage to operate independently at high speed without waiting for previous stages, increasing processing speed. The latches manage the complexity by providing synchronized data transfer and state management between stages.
Solution Approach 2:
The patent replicates identical digital logic circuits across multiple processing stages, creating copies of the same functional units. This copying approach increases processing speed by enabling parallel operations while managing complexity through the use of identical, well-understood circuit designs that can be standardized and optimized.
4Productivity
If identical digital logic circuits are reused through overclocking, then processing efficiency increases, but reliability challenges increase
Solution Approach 1:
The patent employs latches that can be clocked at different frequencies than the data processing operations. This dynamic timing allows the logic circuits to operate at high speeds for efficiency while the latches provide synchronization and stability, managing the reliability implications of high-speed operation through flexible timing control.
Data Source
AI summary
Sets of digital samples associated with received wireless signals are received, each of the sets of digital samples corresponding to a particular RF path. The sets of digital samples are provided to a plurality of pipelines, each of the plurality of pipelines including a plurality of stages, each of the plurality of stages including one or more digital logic circuits. Sets of interconnect data are generated by the plurality of pipelines based on the sets of digital samples, the sets of interconnect data including at least one accumulating value. The sets of interconnect data are passed between adjacent pipelines of the plurality of pipelines along a direction. A result is generated by a last pipeline of the plurality of pipelines based on the at least one accumulating value.