Multi-Standard Interface Circuit With Shared Physical Layer

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Solution Overview

Problem

The proliferation of different interface circuit standards for high-speed performance and portability leads to an increase in parts count due to the need for individual interface circuits conforming to each standard, resulting in inefficiencies and increased complexity.

Innovation Solution

An interface circuit design that includes a shared physical layer module and switch control units to enable compliance with multiple standards such as UFS, M-PCIe, and PCIe, reducing the need for redundant components by sharing modules like the PHY, transaction, and data link modules across standards.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If individual interface circuits are provided for each standard, then compliance with multiple standards is achieved, but parts count increases

Engineering Contradiction:
Improvecompliance with multiple standardsVSAvoidparts count
Core Design Contradiction:
Adaptability or versatilityVSQuantity of substance

Solution Approach 1:

The patent implements a single interface circuit that can operate with multiple interface standards (SATA, SAS, NVLink) by incorporating a standard determination unit that identifies the target standard and configures the interface circuit accordingly. This multi-functional design eliminates the need for separate dedicated circuits for each standard, directly reducing parts count while maintaining compliance with multiple standards.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The interface circuit employs dynamic reconfiguration capability where the circuit's operational parameters and protocol handling are adjusted based on the detected standard type. The standard determination unit dynamically selects appropriate protocol control settings, allowing the same hardware to adapt its behavior to different standards without requiring static dedicated circuits for each standard.

Inventive Principle:
Principle #15Dynamics

2Reliability

If individual interface circuits are provided for each standard, then standard-specific performance is optimized, but device complexity increases

Engineering Contradiction:
Improvestandard-specific performanceVSAvoiddevice complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The interface circuit is segmented into distinct functional units: a standard determination unit that identifies the target standard, and separate protocol control units for different standards (SATA protocol control unit, SAS protocol control unit, NVLink protocol control unit). This segmentation allows each protocol control unit to be optimized for its specific standard while sharing common infrastructure, maintaining standard-specific performance without requiring entirely separate dedicated circuits.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The standard determination unit acts as an intermediary that receives detection signals, identifies the target interface standard, and routes control signals to the appropriate protocol control unit. This mediator architecture enables a single interface circuit to achieve standard-specific optimization by dynamically selecting the appropriate protocol handling path without requiring multiple parallel dedicated circuits.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS9720866B2Interface circuit executing protocol control in compliance with first and second interface standards
Publication Date: 2017.08.01 KIOXIA CORP
  • US9720866B2 patent drawing
  • US9720866B2 patent drawing
  • US9720866B2 patent drawing

AI summary

According to one embodiment, a first module is responsible for protocol control in compliance with a first interface standard. A second module is provided separately from the first module and is responsible for protocol control in compliance with a second interface standard. A third module is responsible for a physical layer shared between the first interface standard and the second interface standard.