Multi-State Resistive Memory Device Structure
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Solution Overview
Problem
Current resistive memory devices are limited to switching between only two states, making them large and costly to manufacture, and there is a need for a more compact and cost-effective memory device capable of switching between multiple states.
Innovation Solution
A memory device structure comprising a first electrode, a first mask element laterally offset from the first electrode, a second electrode, a second mask element laterally offset from the second electrode, and a switching layer between the first and third electrodes, allowing for the formation of multiple memory cells with different resistance states, enabling switching between more than two states.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple memory cells are combined to provide multi-state switching, then the memory capability is improved, but the device size and manufacturing cost increase
Solution Approach 1:
The patent combines multiple memory cells into a single integrated structure where a first memory cell and a second memory cell share common electrodes and switching layers. This merging approach enables multi-state switching capability while reducing the overall device footprint and manufacturing complexity compared to using separate discrete memory cells.
Solution Approach 2:
The intermediate electrode serves multiple functions simultaneously: it acts as the bottom electrode for the first memory cell, the top electrode for the second memory cell, and a common reference point for both cells. This multi-functionality reduces the total number of electrodes required and enables compact multi-state memory operation.
2Adaptability or versatility
If multiple memory cells are combined to provide multi-state switching, then the memory capability is improved, but the manufacturing cost increases
Solution Approach 1:
The patent combines multiple memory cells into a single integrated structure where a first memory cell and a second memory cell share common electrodes and switching layers. This merging approach enables multi-state switching capability while reducing the overall device footprint and manufacturing complexity compared to using separate discrete memory cells.
3Area of stationary object
If a compact memory device structure is used, then the device size is reduced, but the resistance state variability increases
Solution Approach 1:
The patent employs different thicknesses for the first and second switching layers to create locally optimized resistance characteristics. By controlling the thickness of each switching layer independently, the device achieves compact size while maintaining precise control over resistance states and minimizing variability through localized material property optimization.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed memory device structure allows for compact and cost-effective multi-state switching, reducing manufacturing costs and increasing storage capability while minimizing variability in resistance states, enabling neuromorphic computing and multi-bit applications.
Implementation Method 1
The switching layer is normally insulating. However, upon application of a set voltage difference between the electrodes, conducting filaments may be formed within the switching layer and the switching layer thus becomes conductive via the conducting filaments.
Implementation Method 2
A typical resistive memory cell can switch between states based on the resistance of the switching layer. When the switching layer is insulating, the switching layer has a high resistance, and the resistive memory cell may be referred to as being in a high resistance state (HRS).
Data Source
AI summary
A memory device may be provided, including first, second and third electrodes, first and second mask elements and a switching layer. The first mask element may be arranged over a portion of and laterally offset from the first electrode. The second electrode may be arranged over the first mask element. The second mask element may be arranged over the second electrode. The third electrode may be arranged over a portion of and laterally offset from the second mask element. The switching layer may be arranged between the first electrode and the third electrode, along a first side surface of the first mask element, a first side surface of the second electrode and a first side surface of the second mask element.