Multi-State Restore Circuitry for Power Managed Logic Blocks
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Solution Overview
Problem
Existing power management techniques for integrated circuits face challenges in efficiently restoring the state of latches in power-down functional blocks with high overhead in scanning methods and increased complexity and chip real estate requirements for state-saving latches.
Innovation Solution
Designing multi-state restore circuitry that determines and characterizes storage element values during power-down, building restore logic to efficiently restore states with low overhead, using a combination of restorable, state-saving, and don't-care latches, and implementing a restore-state detector and logic cone for effective state restoration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If scan-chain method is used to restore latch states, then state restoration is achieved, but large overhead in clock cycles is incurred
Solution Approach 1:
The invention segments latches into three categories (restorable, state-saving, and don't-care) based on their state restoration requirements. This segmentation allows the system to avoid scanning all latches, thereby reducing clock cycle overhead while still restoring necessary states efficiently.
Solution Approach 2:
Instead of scanning all latches (excessive action), the invention scans only the necessary portion of latches that require state restoration. By identifying and scanning only restorable latches, the system achieves partial action that reduces overhead while maintaining reliability.
2Reliability
If state-saving latches are used for all latches requiring state restoration, then state restoration is ensured, but device complexity and chip real estate requirements increase
Solution Approach 1:
The invention applies local quality by assigning different latch types to different locations based on their specific requirements. Restorable latches use simple scan-chain restoration, state-saving latches use complex state-saving circuitry, and don't-care latches use no restoration. This localized approach reduces overall device complexity while ensuring state restoration where needed.
Solution Approach 2:
The invention uses characterization data that captures the essential state information of latches without requiring full state-saving latches for all cases. By copying only the necessary state characteristics into a compact representation, the system reduces complexity while maintaining restoration capability.
3Measurement precision
If more latches are characterized as restorable with multi-state restore circuitry, then state restoration accuracy improves, but device complexity increases
Solution Approach 1:
The invention changes the parameter of latch characterization by introducing multi-state characterization (different from binary state-saving). This allows more latches to be accurately characterized as restorable with specific restoration requirements, improving restoration accuracy while using compact restore circuitry that doesn't linearly increase complexity.
Data Source
AI summary
Methods of designing and testing restore logic for restoring values to storage elements of power-managed logic circuitry. In one implementation, a design method disclosed includes providing a design of the logic circuitry that, when instantiated, will have a number of states it can be returned to upon repowering-up the logic circuitry. Values held by the storage elements are determined and utilized to categorize the storage elements into categories that allow the development of restore logic that will restore the state of the power-managed logic circuitry that is appropriate to the particular powering-up. The restore logic design is tested by modeling it and the power-managed logic circuitry in a hardware description language and simulating the number of states over a number of test cases. If the design and testing are successful, the restore logic can be optimized for instantiation into an actual integrated circuit.