Multi-Step Etching for Isolation Trench Dielectric Preservation
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Solution Overview
Problem
Conventional manufacturing techniques for non-volatile memory cells often damage the dielectric in trenches, compromising isolation between active areas and leading to potential short circuits due to lack of selectivity in etching processes, especially in stacked gate structures.
Innovation Solution
A method involving the formation of isolation trenches, filling them with a dielectric, and a multi-step etching process to delineate stacked gate structures, where a partial etch of the second polysilicon layer above the trenches is followed by a complete etch of both the polysilicon and gate dielectric layers, preserving dielectric material and maintaining effective isolation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a single etching step is used to remove polysilicon and gate dielectric layers, then the etching process is simple and fast, but the dielectric in trenches is significantly damaged and isolation characteristics are compromised
Solution Approach 1:
The single etching step is divided into two sequential etching steps: a first etching step that removes polysilicon and gate dielectric layers while preserving trench dielectric, and a second etching step that completes the removal process. This segmentation allows selective etching of different materials at different stages, preventing trench dielectric damage while maintaining etching efficiency.
Solution Approach 2:
A preliminary etching step is performed before the complete etching process. This preliminary action selectively removes portions of the polysilicon and gate dielectric layers above active areas while leaving trench dielectric intact, preparing the structure for subsequent etching steps without damaging the isolation regions.
2Reliability
If deeper isolation trenches are employed to reduce dielectric loss effects, then isolation between active areas is improved, but self-aligned source resistance significantly increases and the process becomes impractical for small feature sizes
Solution Approach 1:
The etching parameters are changed between two sequential steps: the first etching step uses parameters selective for polysilicon and gate dielectric that preserve trench dielectric, while the second step uses parameters optimized for complete material removal. This parameter change allows effective isolation with shallower trenches, avoiding the resistance issues associated with deep trenches.
Solution Approach 2:
The multi-step etching process introduces intermediate states where selective materials are removed at different stages. The first etching step acts as an intermediary process that prepares the structure by removing specific layers while protecting trench dielectric, enabling effective isolation without requiring excessive trench depth.
3Ease of manufacture
If conventional etching is used without selectivity between polysilicon and gate dielectric layers, then the etching process is straightforward, but trenches between floating gates are significantly etched and damaged
Solution Approach 1:
The etching process is segmented into multiple steps with different selectivity requirements. The first etching step targets polysilicon and gate dielectric with specific selectivity, while the second step completes the process. This segmentation maintains manufacturing simplicity while achieving precise trench dielectric preservation through controlled selective etching at each stage.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach minimizes dielectric loss in trenches while ensuring sufficient etching to form stacked gate structures, enhancing the isolation between active areas and preventing short circuits, thus improving the reliability of non-volatile memory cells.
Implementation Method 1
partially etching the second polysilicon layer above the isolation trenches, wherein at least a portion of the second polysilicon layer above the isolation trenches remains following the partial etching; and further etching the second polysilicon layer and the gate dielectric layer above the isolation trenches
Data Source
AI summary
Improved methods of manufacturing semiconductor devices are provided to reduce dielectric loss in isolation trenches of the devices. In one example, a method of manufacturing a semiconductor device includes forming a plurality of shallow trench isolation (STI) trenches in a substrate. A tunnel oxide layer, a first conductive layer, a gate dielectric layer, and a second conductive layer are formed above the substrate. The layers are etched to delineate a plurality of stacked gate structures. In particular, the etching may include: performing a first etch of the second conductive layer, wherein at least a portion of the second conductive layer above the STI trenches remains following the first etch; and performing a second etch of the second conductive layer, wherein the remaining portion of the second conductive layer above the STI trenches and portions of the gate dielectric layer above the STI trenches are completely removed by the second etch.