Multi-step Vertical Interconnect for High Aspect Ratio Semiconductor Packaging
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Solution Overview
Problem
Current semiconductor manufacturing processes face challenges in achieving high aspect ratio vertical interconnects with efficient packaging, leading to limitations in miniaturization and increased complexity in electrical interconnection, which hinders the development of smaller, more densely packed semiconductor devices.
Innovation Solution
A multi-step conductive interconnect (MSI) is introduced, comprising a first and second step with specific height and diameter ratios, and a disjointed sidewall profile, along with a method involving multiple layers of photoresist material and redistribution layers to form high aspect ratio vertical interconnects, allowing for improved imaging and plating capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional single-step vertical interconnects are used, then manufacturing process is simpler, but aspect ratio is limited and imaging capability is insufficient
Solution Approach 1:
The vertical interconnect is divided into multiple steps or levels, where each step has a specific height and diameter. This segmentation allows the total height to be distributed across multiple segments, achieving high overall aspect ratio while maintaining manageable dimensions for each individual step that can be imaged and plated effectively.
Solution Approach 2:
The interconnect structure transitions from a simple cylindrical form to a multi-stepped structure with varying diameters at different heights. This dimensional variation creates disjointed sidewall profiles that improve imaging capability by providing better light access and plating surface area, while maintaining the vertical connectivity function.
2Ease of manufacture
If photoresist layer thickness is increased to support plating, then plating capability is improved, but imaging capability deteriorates due to excessive thickness
Solution Approach 1:
The photoresist application is segmented into multiple layers, each with optimized thickness for both imaging and plating support. By stacking multiple thinner photoresist layers rather than using one thick layer, the structure achieves sufficient plating capability while maintaining imaging capability, as each layer remains within the optimal thickness range for photolithography.
3Productivity
If semiconductor devices are miniaturized, then power consumption is reduced and performance is improved, but electrical interconnection complexity increases
Solution Approach 1:
The interconnect structure uses vertical height and stepped diameter variations to achieve complex interconnection functions without increasing lateral footprint. By utilizing the vertical dimension and creating disjointed sidewall profiles, the design accommodates miniaturized device dimensions while maintaining effective electrical interconnection capability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The MSI enables the creation of semiconductor devices with higher aspect ratios, facilitating more compact and efficient electrical interconnections, thereby supporting the production of smaller, more densely packed semiconductor devices with enhanced performance and reduced manufacturing complexity.
Implementation Method 1
A first layer of photoresist material is disposed over the first build-up interconnect structure and first openings are formed in the first layer of photoresist material
Implementation Method 2
first steps of the MSIs may be formed by disposing conductive material within the first openings in the first layer of photoresist material
Data Source
AI summary
A multi-step conductive interconnect (MSI) may comprise a first step of the MSI comprising a first end and a second end opposite the first end, a first height (Ha) and a first diameter (Da). A second step of the MSI may comprise a first end and a second end opposite the first end. The first end of the second step contacts the second end of the first step. The second step may comprise a second height (Hb) and a second diameter (Db). The MSI may comprise a height (H) and a height to width aspect ratio (H:Da) greater than or equal to 1.5:1. A sidewall of the first step may comprise an offset (O) with respect to a sidewall of the second step to form a disjointed sidewall profile. The offset O may be in a range of 0.1 μm-20 μm.