Multi-Stream Image Processing Using One Time-Divided Circuit

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Solution Overview

Problem

The high cost associated with using multiple latter stage circuits for processing multiple image streams is a challenge in existing image processing technologies.

Innovation Solution

A multi-stream image processing apparatus and method that utilizes a single latter stage circuit with a time-division method to process multiple image streams, employing a synchronization circuit to coordinate the storage and retrieval of image frames across different resolution levels.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If multiple latter stage circuits are used to process multiple image streams, then processing capability is improved, but hardware cost increases

Engineering Contradiction:
Improveprocessing capabilityVSAvoidhardware cost
Core Design Contradiction:
ProductivityVSQuantity of substance

Solution Approach 1:

The patent implements time-division multiplexing where a single latter stage circuit processes multiple image streams sequentially in different time slots. The circuit alternates between processing high-resolution streams and low-resolution streams, achieving multi-stream processing capability without requiring multiple parallel circuits, thus reducing hardware cost while maintaining processing capability.

Inventive Principle:
Principle #19Periodic action

Solution Approach 2:

The latter stage circuit is designed to handle multiple types of image streams (different resolutions, different formats) through a universal processing architecture. By making the circuit multi-functional and adaptable to various stream types, the system eliminates the need for dedicated circuits for each stream type, reducing overall hardware requirements.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Productivity

If multiple latter stage circuits are used to process multiple image streams, then processing capability is improved, but device complexity increases

Engineering Contradiction:
Improveprocessing capabilityVSAvoiddevice complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The system uses periodic time-division multiplexing to simplify the device architecture. Instead of managing multiple parallel circuits simultaneously, a single circuit operates periodically on different streams, reducing interconnections, control logic, and synchronization complexity while maintaining the ability to process multiple streams.

Inventive Principle:
Principle #19Periodic action

Solution Approach 2:

The patent merges multiple processing functions into a single latter stage circuit by combining the processing paths for different image streams into one unified circuit. This consolidation reduces the number of components, interconnections, and control mechanisms, thereby simplifying the overall device complexity.

Inventive Principle:
Principle #5Merging (Combining)

3Productivity

If memory is allocated for each image stream, then processing efficiency is improved, but memory cost increases

Engineering Contradiction:
Improveprocessing efficiencyVSAvoidmemory cost
Core Design Contradiction:
ProductivityVSQuantity of substance

Solution Approach 1:

The memory system implements time-division multiplexing where a single memory resource is allocated to different image streams in periodic time slots. The memory is dynamically assigned to high-resolution streams during their designated time periods and to low-resolution streams during other periods, eliminating the need for separate dedicated memory for each stream while maintaining processing efficiency.

Inventive Principle:
Principle #19Periodic action

Data Source

PatentEP3675028B1Multi-stream image processing apparatus and method of the same
Publication Date: 2025.07.16 SIGMASTAR TECH LTD
  • EP3675028B1 patent drawingFigure 1
  • EP3675028B1 patent drawingFigure 2
  • EP3675028B1 patent drawingFigure 3

AI summary

The present disclosure discloses a multi-stream image processing method that includes steps outlined below. Image streams that include a main image stream and at least one sub image stream are generated by a former stage circuit, wherein a resolution of the main image stream is higher than the resolution of the sub image stream. Within an image frame processing time period, a N-th sub image frame is stored in a current sub image storage block in a memory module and a N-th main image frame is stored in a current main image storage block in the memory module by the former stage circuit. Within a first sub period of the image frame processing time period, a N-1-th sub image frame is read from a former sub image storage block in the memory module by a latter stage circuit to perform processing. Within a second sub period of the image frame processing time period, the N-th main image frame is read by the latter stage circuit to perform processing.