Boolean Model for Multi-Path and Multi-Strength Signal Verification
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Solution Overview
Problem
Traditional equivalence checking techniques are inadequate for verifying circuits with multiple levels of input/output paths, such as FPGA, ROM arrays, and RAM circuits, as they fail to accurately represent multi-strength signals and potential collisions, leading to undetected errors.
Innovation Solution
A method and system for creating a Boolean model of multi-path and multi-strength signals that involves reading a design description, replacing multi-strength devices with logic including encoded output signals, applying strength resolution logic, and using a Boolean algorithm to verify circuit equivalence.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional Boolean equivalence checking is used, then verification simplicity is maintained, but accuracy of multi-strength signal representation deteriorates
Solution Approach 1:
The patent segments the verification model into multiple components: strength encoding logic that assigns binary codes to different signal strengths, multi-path detection logic that identifies parallel signal paths, and collision detection logic that flags potential conflicts. This segmentation allows accurate representation of multi-strength signals while maintaining manageable complexity through modular processing.
Solution Approach 2:
The patent adds a new dimension to traditional Boolean verification by incorporating strength encoding. Instead of simple binary logic levels, the system uses encoded binary values to represent multiple signal strengths (e.g., strong, weak, floating, disconnected). This dimensional expansion enables accurate representation of analog-like signal characteristics within a digital verification framework.
2Reliability
If multi-strength devices are abstracted as Boolean functions, then device complexity is reduced, but reliability of collision detection deteriorates
Solution Approach 1:
The patent introduces an intermediary encoding layer between the physical multi-strength devices and the Boolean verification logic. Strength encoding logic acts as a mediator that translates multi-strength signal characteristics into encoded binary values, which can then be processed by extended Boolean algorithms. This intermediary layer preserves collision detection reliability while allowing the use of systematic verification methods.
Solution Approach 2:
The patent changes the parameters of the verification algorithm to accommodate multi-strength signals. Instead of standard Boolean equivalence checking, the system uses extended algorithms that incorporate strength encoding comparison, multi-path analysis, and collision detection based on encoded values. This parameter change enables reliable collision detection in circuits with multiple signal strength levels.
3Adaptability or versatility
If formal verification is applied to circuits with multiple input/output paths, then verification thoroughness is improved, but applicability deteriorates due to inability to handle multi-strength signals
Solution Approach 1:
The patent creates a universal verification framework that can handle both traditional single-path Boolean circuits and complex multi-path circuits with multi-strength signals. The extended Boolean algorithm incorporates strength encoding, multi-path detection, and collision detection capabilities, making it applicable to a broader range of circuit types while maintaining formal verification thoroughness.
Solution Approach 2:
The patent replaces the mechanical limitation of traditional Boolean algebra with an extended mathematical framework. By substituting standard Boolean operations with extended algorithms that operate on encoded strength values, the system achieves both broad applicability to multi-path circuits and precise signal behavior analysis through formal equivalence checking.
Data Source
AI summary
A system, method, computer program product for verification and equivalence checking. In one approach, the system, method, and computer program product analyzes the switching paths in a manner consistent with circuit functionality to provide a complete application which can verify the complex characteristics in the circuits to the accurate RTL model function, including FPGA, ROM Arrays, RAM circuits, and other custom integrated circuit designs.