Multi-substrate Electro-Optical Interconnection Thermal Management
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Solution Overview
Problem
Existing electro-optical multi-chip interconnection systems face limitations such as limited usable electronic dies due to silicon photonic chip size, handling difficulties of large silicon interposers, high heat dissipation requirements, and sensitivity to temperature variations, which hinder efficient high-speed data transmission and thermal management.
Innovation Solution
The solution involves arranging dissipative electronic chips side-by-side alongside a photonic waveguide fabric silicon die, with integrated transceiver circuit dies electrically coupled through a multi-chip module primary substrate, allowing for efficient thermal separation and high-speed optical data transmission between ICs, using a photonic waveguide fabric silicon die with defined waveguides and devices for optical modulation and detection, and electrical transceiver dies integrated with control circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If electronic dies are mounted close to laser diode array chip on silicon photonic interposer, then optical interconnectivity is improved, but heat dissipation becomes unmanageable due to high temperature requirements
Solution Approach 1:
The system separates electronic components into distinct modules: laser diode array chips, electronic dies for signal processing, and transceiver circuits, each mounted on appropriate substrates (PCB or silicon photonic interposer) rather than combining all on a single platform, thereby isolating heat-generating components
Solution Approach 2:
The patent introduces intermediate substrates and mounting structures between heat-generating laser diodes and temperature-sensitive electronic dies, using the PCB and interposer architecture as thermal buffers while maintaining optical connectivity through waveguide coupling
2Productivity
If large silicon photonic interposers with dense through silicon vias are used, then electrical connectivity is improved, but handling and assembly difficulty increases
Solution Approach 1:
The system divides the interconnection function across multiple components: the PCB provides basic electrical connectivity, while the silicon photonic interposer provides optical waveguides and selective electrical connections, allowing each to be optimized independently for its specific function
Solution Approach 2:
The patent transitions from planar 2D mounting to 3D vertical stacking with through-silicon vias, enabling electrical and optical connections to pass through the interposer thickness, thereby achieving high-density connectivity without increasing lateral footprint or handling complexity
3Quantity of substance
If maximum area CMOS mask (800 mm2) is used for silicon photonic chip, then number of electronic dies is increased, but chip size and complexity increase
Solution Approach 1:
The system distributes electronic functions across multiple separate dies mounted on the PCB and interposer rather than integrating all functions into a single large chip, allowing standard-sized CMOS masks to be used while achieving high component counts through modular assembly
Solution Approach 2:
The silicon photonic interposer serves multiple functions simultaneously: it provides optical waveguides for light transmission, electrical connections through TSVs, mechanical support, and thermal management, thereby reducing the need for separate dedicated components and simplifying the overall system architecture
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables efficient high-speed data transmission above 10 Gbps, simplifies heat management, and increases the number of interconnected ICs, overcoming the limitations of prior art architectures by promoting effective thermal separation and scalable interconnectivity.
Implementation Method 1
The optical transmission is inside the silicon photonics die
Implementation Method 2
grating couplers used to couple light in and out of optical I/O fibers
Implementation Method 3
Through silicon vias (TSV) created in the photonic interposer provide the electrical path to/from the PCB substrate and the optoelectronic devices inside the silicon photonics die
Implementation Method 4
laser diode array chip
Data Source
AI summary
An intra-board chip-to-chip optical communications system has a high bit rate and high data throughput based on the use of a silicon photonic interposer. The system includes a multi-substrate electro-optical structure for communications with CMOS and/or BiCMOS IC chips of a PCB. The structure includes a multi-chip module primary substrate mounted over the supporting PCB. The multi-chip module primary substrate implements high frequency electrical interconnections between transceiver circuit chips, mounted on the silicon photonic interposer, and the IC chips.