Multi-substrate Region-based Semiconductor Package Design
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Solution Overview
Problem
Conventional semiconductor packages, such as leadframe-based and BGA packages, face limitations in providing increased I/O connections, compatibility, and heat dissipation, and are not cost-effective or reliable, especially with the advancement of electronic products towards higher density and lower profiles.
Innovation Solution
A multi-substrate region-based package is developed, where a chip is divided into functional regions with independent electrical connecting portions, each mounted with substrates having bond pads and electrical connecting portions, encapsulated with a layer exposing the bond pads, and optionally integrated with sub-chips, allowing for increased yield, compatibility, and improved heat dissipation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional leadframe-based package is used, then the structure is simple and manufacturing is easy, but the number of I/O connections is limited by the size of the encapsulant
Solution Approach 1:
The package is divided into multiple functional regions (first region, second region, third region) with different substrate configurations. The first region uses a leadframe substrate for I/O connections, the second region uses a substrate for heat dissipation, and the third region uses a substrate for additional I/O connections. This segmentation allows each region to optimize for its specific function, increasing the total number of I/O connections without proportionally increasing the overall package size.
Solution Approach 2:
The patent utilizes the Z-direction (vertical dimension) by stacking multiple substrates and functional regions vertically. The chip is mounted on the leadframe substrate, with additional substrates positioned above and below the chip in different regions. This three-dimensional arrangement increases I/O connection density without expanding the horizontal footprint of the encapsulant.
2Quantity of substance
If BGA package configuration is used to increase I/O connections, then more I/O connections can be obtained, but compatibility with lower profile and shorter life span requirements is poor
Solution Approach 1:
Different regions of the package are assigned different substrate types and functions tailored to local requirements. The first region (with leadframe substrate) provides traditional I/O connections compatible with existing designs, the second region (with heat dissipation substrate) addresses thermal management for high-performance applications, and the third region (with additional substrate) provides extra I/O connections. This local optimization allows the package to meet diverse requirements including lower profile and shorter life span applications while providing increased I/O connections.
3Area of stationary object
If high-density packaging technologies are used to reduce package size, then smaller packaging area is achieved, but heat dissipation becomes more difficult
Solution Approach 1:
The package is segmented into functional regions with dedicated heat dissipation capabilities. The second region specifically incorporates a substrate designed for heat dissipation, positioned to thermally couple with the chip. This segmentation ensures that heat management is addressed in a dedicated zone without compromising the high-density packaging achieved in other regions.
Solution Approach 2:
Heat dissipation is addressed in the Z-direction by positioning heat dissipation substrates above and below the chip in the second region. This vertical heat dissipation path allows efficient thermal management without increasing the horizontal packaging area, maintaining the compact footprint while effectively managing heat.
4Adaptability or versatility
If multiple chips are integrated in SiP to maintain compatibility, then good compatibility among different chips is achieved, but packaging complexity increases
Solution Approach 1:
The package uses a segmented approach with three distinct functional regions, each with simplified substrate configurations. Rather than integrating multiple different chips in a complex SiP architecture, the patent segments the package into regions that can accommodate different chip types and substrate configurations. This segmentation simplifies the packaging process for each region while maintaining overall compatibility.
Data Source
AI summary
A multi-substrate region-based package and a method for fabricating the same are provided. An active surface of a chip is divided into a plurality of functional regions, and each of the functional regions is electrically connected to a corresponding substrate via bonding wires. Each of the functional regions has a separate system, and the circuit layout thereof is not limited by the substrate or other systems but can be flexibly and independently designed, thereby allowing the package to be made smaller and thinner. Each set of the functional region and its corresponding substrate functions as an independent unit, such that the substrates are not affected by each other, thereby providing good compatibility, improved reliability and reduced packaging area.