Multi-Supply GPIO Circuit for Cross-Voltage IC Interfaces
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Solution Overview
Problem
Integrated circuits designed for multiple computing functions face challenges in operating with devices that have different physical specifications, particularly due to varying voltage levels, requiring manufacturer-specific circuits or multiple circuit designs to accommodate different supply modes.
Innovation Solution
The integrated circuit is configured with multiple power supply modes, including core circuitry and chip connection points that facilitate communication with external circuits operating in different voltage levels, using multi-supply mode GPIO drivers and electrostatic discharge circuitry to prevent large currents, allowing connection to external circuits with minimal configuration changes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a single integrated circuit is designed to operate with multiple external circuits having different voltage levels, then adaptability is improved, but device complexity increases due to the need for multiple power supply modes and configuration options
Solution Approach 1:
The integrated circuit is designed with universal support for multiple supply modes (1.2V, 1.8V, 3.3V) through a unified architecture. The GPIO drivers and power management circuits can operate across different voltage levels without requiring separate dedicated circuits for each voltage level, enabling a single chip to interface with external devices operating at various voltages.
Solution Approach 2:
The circuit employs configurable parameters including supply mode selection (1.2V/1.8V/3.3V), pull-up resistor values (2kΩ, 10kΩ, 50kΩ), and drive strength settings. These parameters can be adjusted via configuration registers or hardware controls, allowing the same physical circuit to adapt its electrical characteristics to match different external devices without physical reconfiguration.
2Adaptability or versatility
If manufacturer-specific circuits are used to accommodate different supply modes, then compatibility with specific devices is improved, but ease of manufacture deteriorates due to the need for multiple circuit designs
Solution Approach 1:
Rather than producing different circuit designs for different voltage requirements, the patent implements a universal circuit architecture that can operate at 1.2V, 1.8V, or 3.3V supply modes. This single design approach simplifies manufacturing by eliminating the need to produce multiple versioned circuits, while still achieving compatibility with devices across different voltage standards.
Solution Approach 2:
The circuit incorporates dynamic voltage scaling capabilities where the operating voltage and current parameters can be adjusted during operation based on the connected external device. This dynamic adaptation allows the same manufactured circuit to serve multiple voltage requirements without requiring separate manufacturing processes for each voltage level.
3Reliability
If electrostatic discharge circuitry is added to prevent large currents, then reliability is improved, but device complexity increases
Solution Approach 1:
The electrostatic discharge (ESD) protection circuitry is integrated into the existing GPIO driver structure rather than being added as separate external components. The ESD protection diodes and clamping circuits are merged with the pull-up resistors and driver transistors, providing current protection functionality within the same circuit block without requiring additional discrete components or separate protection circuits.
Data Source
AI summary
Systems and methods are provided for a multiple power supply mode input/output (IO) circuit of an integrated circuit that includes a plurality of power rails, one or more supply mode power rails being associated with each supply mode of the integrated circuit, and a core power rail being associated with core circuitry of the integrated circuit. The IO circuit may further include a plurality of chip connection points, each chip connection point being connected to one or more of the power rails, the chip connection points being configured for connection to one or more package connection points.