Multi-Supply Sequential Logic for Low-Vmin Clock Timing

Solution Overview

Problem

Sequential logic units in processors experience increased clock-to-output delay and degraded performance when operating at minimum operating voltage (Vmin), particularly affecting flip-flops and other sequential logic gates, leading to reduced power supply levels.

Innovation Solution

Implementing a multi-supply sequential logic unit where the clock signal path operates on a higher power supply level than the data signal path, using a level-shifter to boost the clock signal and reduce data contention, thereby improving timing parameters and reducing power consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of energy

If sequential logic gates are operated on minimum operating voltage (Vmin) to reduce power dissipation, then power consumption is reduced, but clock-to-output delay increases and performance degrades

Engineering Contradiction:

Improvepower dissipationVSAvoidclock-to-output delay

Core Design Contradiction:

Loss of energyVSLoss of time

Solution Approach 1:

The sequential logic unit is divided into two separate power supply domains: the data path operates on Vmin (first power supply level) while the clock path operates on a higher voltage (second power supply level). This segmentation allows each path to be optimized independently for its specific function, reducing overall power consumption while maintaining timing performance.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Different power supply levels are applied to different functional regions of the sequential logic unit. The clock path receives a higher power supply level specifically where needed to drive timing-critical signals, while the data path operates at lower voltage for power efficiency. This local differentiation resolves the contradiction by providing high performance only where temporally critical.

Inventive Principle:

Principle #3Local quality

2Loss of energy

If sequential logic gates are operated on minimum operating voltage (Vmin) to reduce power dissipation, then power consumption is reduced, but setup time increases

Engineering Contradiction:

Improvepower dissipationVSAvoidsetup time

Core Design Contradiction:

Loss of energyVSReliability

Solution Approach 1:

The sequential logic unit is divided into two separate power supply domains: the data path operates on Vmin (first power supply level) while the clock path operates on a higher voltage (second power supply level). This segmentation allows each path to be optimized independently for its specific function, reducing overall power consumption while maintaining timing performance.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Different power supply levels are applied to different functional regions of the sequential logic unit. The clock path receives a higher power supply level specifically where needed to drive timing-critical signals, while the data path operates at lower voltage for power efficiency. This local differentiation resolves the contradiction by providing high performance only where temporally critical.

Inventive Principle:

Principle #3Local quality

3Device complexity

If a single power supply level is used for both clock and data paths, then device complexity is reduced, but clock-to-output delay increases due to data contention

Engineering Contradiction:

Improvepower supply configurationVSAvoidclock-to-output delay

Core Design Contradiction:

Device complexityVSLoss of time

Solution Approach 1:

The sequential logic unit is divided into two separate power supply domains: the data path operates on Vmin (first power supply level) while the clock path operates on a higher voltage (second power supply level). This segmentation allows each path to be optimized independently for its specific function, reducing overall power consumption while maintaining timing performance.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Different power supply levels are applied to different functional regions of the sequential logic unit. The clock path receives a higher power supply level specifically where needed to drive timing-critical signals, while the data path operates at lower voltage for power efficiency. This local differentiation resolves the contradiction by providing high performance only where temporally critical.

Inventive Principle:

Principle #3Local quality

Data Source

PatentUS8901819B2Multi-supply sequential logic unit

Publication Date: 2014.12.02 INTEL CORP

AI summary

Described herein are apparatus, method, and system for reducing clock-to-output delay of a sequential logic unit in a processor. The apparatus comprises a sequential unit including: a data path, to receive an input signal, including logic gates to operate on a first power supply level, the data path to generate an output signal; and a clock path including logic gates to operate on a second power supply level, the logic gates of the clock path to sample the input signal using a sampling signal to generate the output signal, wherein the second power supply level is higher than the first power supply level. The apparatus improves (i.e. reduces) setup time of the sequential unit and allows the processor to operate at minimum operating voltage (Vmin) without degrading performance of the sequential unit.