Multi-Supply Sequential Logic for Lower Clock-to-Output Delay
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Solution Overview
Problem
Sequential logic units in processors experience degraded performance and increased clock-to-output delay when operating at minimum operating voltage (Vmin), leading to inefficiencies in power consumption and timing parameters.
Innovation Solution
Implementing a multi-supply sequential logic unit where the clock signal path operates on a higher power supply level than the data signal path, using a level-shifter to convert the clock signal and reduce data contention, thereby enhancing the clock-to-output delay and timing parameters.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If sequential logic gates operate on minimum operating voltage (Vmin) to reduce power dissipation, then power consumption is reduced, but clock-to-output delay increases and performance degrades
Solution Approach 1:
The sequential logic unit is divided into two separate power supply domains: the data path operates on Vmin (first power supply level) while the clock path operates on a higher voltage level (second power supply level). This segmentation allows each path to be optimized independently for its specific function, reducing overall power consumption while maintaining timing performance.
Solution Approach 2:
Different power supply levels are applied to different functional regions of the sequential logic unit. The clock path receives a higher power supply level to ensure fast switching and minimal delay, while the data path operates at Vmin to minimize power dissipation. This local differentiation of power quality resolves the contradiction between power savings and timing performance.
2Loss of energy
If sequential logic gates operate on minimum operating voltage (Vmin) to reduce power dissipation, then power consumption is reduced, but setup time increases
Solution Approach 1:
The sequential logic unit is divided into two separate power supply domains: the data path operates on Vmin (first power supply level) while the clock path operates on a higher voltage level (second power supply level). This segmentation allows each path to be optimized independently for its specific function, reducing overall power consumption while maintaining timing performance.
Solution Approach 2:
Different power supply levels are applied to different functional regions of the sequential logic unit. The clock path receives a higher power supply level to ensure fast switching and minimal delay, while the data path operates at Vmin to minimize power dissipation. This local differentiation of power quality resolves the contradiction between power savings and timing performance.
3Device complexity
If a single power supply level is used for both clock and data paths, then device complexity is reduced, but clock-to-output delay increases due to data contention
Solution Approach 1:
The sequential logic unit is divided into two separate power supply domains: the data path operates on Vmin (first power supply level) while the clock path operates on a higher voltage level (second power supply level). This segmentation allows each path to be optimized independently for its specific function, reducing overall power consumption while maintaining timing performance.
Solution Approach 2:
Different power supply levels are applied to different functional regions of the sequential logic unit. The clock path receives a higher power supply level to ensure fast switching and minimal delay, while the data path operates at Vmin to minimize power dissipation. This local differentiation of power quality resolves the contradiction between power savings and timing performance.
Data Source
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AI summary
Described herein are apparatus, method, and system for reducing clock-to-output delay of a sequential logic unit in a processor. The apparatus comprises a sequential unit including: a data path, to receive an input signal, including logic gates to operate on a first power supply level, the data path to generate an output signal; and a clock path including logic gates to operate on a second power supply level, the logic gates of the clock path to sample the input signal using a sampling signal to generate the output signal, wherein the second power supply level is higher than the first power supply level. The apparatus improves (i.e. reduces) setup time of the sequential unit and allows the processor to operate at minimum operating voltage (Vmin) without degrading performance of the sequential unit.