Multi-Surface Packaging Substrate Layout for Higher Pin Density
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Solution Overview
Problem
The increasing number of connection structures on packaging substrates leads to larger packaging sizes, causing thermal deformation and challenges in connecting pins to printed circuit boards.
Innovation Solution
The packaging substrate design includes a body with first, second, and side surfaces, utilizing metal cabling to connect first and third connection structures on the side and first surfaces, allowing pins to be distributed across multiple surfaces, reducing the need for pins on the second surface and minimizing packaging size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the quantity of first connection structures at the first surface increases, then the connectivity of the packaging substrate is improved, but the packaging size increases
Solution Approach 1:
The patent applies dimensionality change by distributing connection structures not only on the first and second surfaces but also on the side surface of the packaging substrate. This three-dimensional arrangement allows pins to be positioned on multiple surfaces, increasing connectivity without requiring a larger planar area, thus resolving the contradiction between improved connectivity and increased packaging size.
2Quantity of substance
If the packaging size increases, then more pins can be accommodated, but thermal deformation of the chip occurs
Solution Approach 1:
By utilizing the side surface in addition to the top and bottom surfaces, the patent accommodates more pins within a compact footprint. This reduces the overall packaging size and minimizes thermal deformation risks while maintaining the required number of pins through spatial optimization.
3Ease of manufacture
If pins are concentrated on the second surface, then connection to printed circuit board is simplified, but packaging substrate area increases
Solution Approach 1:
The patent distributes pins across the first surface, second surface, and side surface. This multi-surface arrangement reduces the concentration of pins on any single surface, allowing for a more compact substrate area while maintaining manufacturing feasibility through organized connection structures on each surface.
4Area of stationary object
If the quantity of pins at the second surface is reduced, then packaging size is minimized, but connectivity to peripheral circuits must be maintained
Solution Approach 1:
The patent compensates for reduced pins on the second surface by adding connection structures on the side surface and optimizing the first surface layout. This three-dimensional distribution maintains total connectivity requirements while reducing the area dedicated to pins on any single surface, thereby minimizing overall packaging size.
Data Source
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AI summary
Embodiments of this application disclose a packaging substrate, a packaging structure, an electronic device, and a manufacturing method, and pertain to the field of chip packaging technologies. The packaging substrate includes a body. The body includes metal cabling. The body includes a first surface, a second surface, and a side surface. The side surface is connected to the first surface and the second surface. The first surface includes a plurality of first connection structures. The second surface includes second connection structures. The side surface includes third connection structures. A part of the plurality of first connection structures are connected to the second connection structures by using the metal cabling. The other part of the plurality of first connection structures are connected to the third connection structures by using the metal cabling. When the same total quantity of pins need to be disposed, a part of the pins are transferred to the side surface of the body, to reduce a quantity of pins at the second surface. In this way, when packaging is performed on a die, a packaging substrate with a smaller area may be used, to reduce a packaging size.