Multi-Synchronizer Circuit for Debugging Multi-Domain Signals
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Solution Overview
Problem
Existing systems for debugging circuits with multiple clock domains require complex synchronizer designs and significant resources, often failing to capture events occurring simultaneously across different clock domains due to frequency and phase differences.
Innovation Solution
A single integrated logic analyzer with multiple instances of a multi-synchronizer circuit synchronizes unsynchronized trigger signals from various clock domains, evaluates a trigger equation based on synchronized signals, and stores trigger markers and signal states in memory, reducing resource requirements and complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If complex synchronizer designs are used to capture events across multiple clock domains, then reliability of capturing events is improved, but device complexity increases
Solution Approach 1:
The synchronizer is divided into multiple independent instances, each handling a specific clock domain transition. Each instance contains a dedicated set of flip-flops for synchronizing signals from a specific source clock domain to a destination clock domain, eliminating the need for a single complex synchronizer that would need to handle all clock domains simultaneously.
Solution Approach 2:
The patent introduces an intermediary selection mechanism that chooses which synchronizer instance output to use based on trigger conditions. The selection logic acts as an intermediary between multiple synchronizer instances and the final trigger evaluation, allowing the system to reliably capture events from different clock domains without requiring all synchronizers to be active simultaneously, thus reducing overall complexity.
2Adaptability or versatility
If multiple synchronizer circuits are used to handle multiple clock domains, then adaptability to different clock domains is improved, but quantity of circuit resources increases
Solution Approach 1:
Each synchronizer instance is designed as a universal module that can synchronize signals from any source clock domain to any destination clock domain. The synchronizer instances use the same internal structure (flip-flops and logic) but are configured differently through selection logic, allowing the system to adapt to different clock domain combinations without requiring unique circuit designs for each scenario.
Solution Approach 2:
The system dynamically selects which synchronizer instance to use based on the current trigger conditions and clock domain requirements. The selection logic enables the system to activate only the necessary synchronizer instances for a given debugging scenario, reducing the effective resource usage while maintaining the capability to handle any clock domain combination when needed.
3Device complexity
If a single integrated logic analyzer is used instead of multiple separate analyzers, then device complexity is reduced, but measurement precision across multiple clock domains may worsen
Solution Approach 1:
The single integrated logic analyzer is segmented into multiple independent synchronizer instances, each responsible for a specific clock domain transition. This segmentation allows the analyzer to maintain precise measurement capabilities for each clock domain while operating within a unified, less complex system architecture.
Solution Approach 2:
The selection logic within the integrated analyzer acts as an intermediary that ensures precise event capture by routing signals from the appropriate synchronizer instance based on trigger conditions. This intermediary mechanism maintains measurement precision equivalent to multiple separate analyzers while benefiting from the reduced complexity of a single integrated system.
Data Source
AI summary
Disclosed approaches for probing signals in a plurality of clock domains include inputting unsynchronized trigger signals from the plurality of clock domains to a plurality of instances of a multi-synchronizer circuit, respectively. Each instance of the multi-synchronizer circuit includes a plurality of synchronizer circuits. One or more of the plurality of synchronizer circuits synchronizes the respective unsynchronized trigger signal with one clock signal from the plurality of clock domains. Output of one of the one or more synchronizer circuits in each instance of the multi-synchronizer circuit is selected as a respective synchronized trigger signal. A trigger equation is evaluated based on a state of each respective synchronized trigger signal. A final trigger signal is generated based the evaluating of the trigger equation, a trigger marker is stored in a memory in response to a state of the final trigger signal, and states of probed signals are stored in the memory.