Multi-taken Entry Prediction Circuitry for Instruction Flow
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Solution Overview
Problem
The existing prediction circuitry in data processing apparatuses has limited throughput, which affects the speed at which instructions are identified for execution, and increasing throughput without compromising accuracy is a challenge, especially for instruction flow changing instructions that cause discontiguous changes in the address space.
Innovation Solution
The introduction of a multi-taken entry in the target prediction storage allows for predicting a series of instructions exhibiting static behavior, enabling the prediction circuitry to skip making predictions for these instructions and start from the target address, thereby increasing throughput without reducing accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If prediction circuitry processes each instruction individually, then prediction accuracy is maintained, but throughput is limited
Solution Approach 1:
The patent merges multiple sequential instructions into a single prediction entry by detecting static behavior patterns. When instructions exhibit static behavior (same execution path each time), the prediction circuitry groups them together and processes them as one unit, thereby increasing throughput while maintaining accuracy for these predictable instruction sequences.
Solution Approach 2:
The prediction circuitry performs preliminary analysis to identify instructions with static behavior before full prediction processing. By pre-detecting which instructions will always execute the same path, the system can skip detailed prediction processing for those instructions and proceed directly to the next prediction task, reducing overall processing time.
2Speed
If prediction circuitry increases throughput, then instruction identification speed improves, but prediction accuracy may deteriorate
Solution Approach 1:
The patent applies different prediction strategies to different instruction groups based on their behavior characteristics. For instructions with static behavior, the system uses simplified processing (higher speed, lower computational overhead). For instructions with dynamic behavior, the system uses detailed prediction analysis (lower speed, higher accuracy). This local differentiation allows the system to optimize both speed and accuracy where appropriate.
3Productivity
If all instructions require prediction processing, then prediction accuracy is maintained, but fetch queue throughput is limited
Solution Approach 1:
The prediction circuitry extracts and separates instructions with static behavior from the general instruction stream. These extracted instructions are then processed differently - grouped into entries and processed in bulk rather than individually - which reduces the overall processing complexity while maintaining the ability to accurately predict instruction flow.
Data Source
AI summary
An apparatus and method are provided for making predictions for instruction flow changing instructions. The apparatus has a fetch queue that identifies a sequence of instructions to be fetched for execution by execution circuitry, and prediction circuitry for making predictions in respect of instruction flow changing instructions, and for controlling which instructions are identified in the fetch queue in dependence on the predictions. The prediction circuitry has a target prediction storage used to identify target addresses for instruction flow changing instructions that are predicted as taken. The target prediction storage comprises at least one entry that is configurable as a multi-taken entry to indicate that a source instruction flow changing instruction identified by that entry is a first instruction flow changing instruction with an associated first target address that identifies a series of instructions that is expected to exhibit static behaviour and that terminates with a second instruction flow changing instruction, where the second instruction flow changing instruction is unconditionally taken and has an associated second target address. The prediction circuitry is arranged, when making a prediction for a chosen instruction flow changing instruction that is identified by a multi-taken entry in the target prediction storage, to identify with reference to target address information stored in that multi-taken entry both the series of instructions and a target instruction at the second target address. It then causes the series of instructions and the target instruction to be identified in the fetch queue, and begins making further predictions starting from the target instruction at the second target address.