Multi-Tap DFFE Equalizer for Precursor and Postcursor ISI

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Solution Overview

Problem

Traditional SerDes architectures face limitations in coupling between clock data recovery (CDR) and equalization adaptation, leading to sub-optimal CDR locking points and increased sensitivity to transmitter settings, with DFE being limited to postcursor ISI correction and prone to noise amplification by FFE.

Innovation Solution

A SerDes receiver architecture integrating a Decision Feedforward Equalizer (DFFE) for both precursor and postcursor ISI correction, decoupling CDR and equalization adaptations, and using a multi-tap DFFE topology to achieve symmetric pulse responses and improved noise resilience.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If FFE is used for precursor and postcursor ISI correction, then ISI correction capability is improved, but noise and crosstalk are amplified

Engineering Contradiction:
ImproveISI correction capabilityVSAvoidnoise amplification
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The equalizer is segmented into multiple independent DFFE stages, each handling specific ISI components. The first stage corrects precursor ISI while subsequent stages correct postcursor ISI, allowing selective noise management for different ISI types without uniform noise amplification across all correction functions.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different equalization approaches are applied to different time domains: DFFE is used specifically for precursor ISI correction where noise amplification is problematic, while traditional FFE is used for postcursor ISI where noise amplification is less critical. This local differentiation optimizes the noise-ISI tradeoff in each domain.

Inventive Principle:
Principle #3Local quality

2Object-affected harmful factors

If DFE is used for postcursor ISI correction, then noise amplification is avoided, but precursor ISI correction capability is lost

Engineering Contradiction:
Improvenoise amplification avoidanceVSAvoidprecursor ISI correction capability
Core Design Contradiction:
Object-affected harmful factorsVSReliability

Solution Approach 1:

The equalizer is segmented into multiple independent DFFE stages, each handling specific ISI components. The first stage corrects precursor ISI while subsequent stages correct postcursor ISI, allowing selective noise management for different ISI types without uniform noise amplification across all correction functions.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The DFFE combines the advantages of both FFE and DFE by merging the precursor ISI correction capability of FFE with the noise-free postcursor ISI correction of DFE in a unified multi-stage architecture, achieving comprehensive ISI correction without the drawbacks of either approach alone.

Inventive Principle:
Principle #5Merging (Combining)

3Reliability

If multiple taps of FFE are used for ISI correction, then both precursor and postcursor ISI are corrected, but device complexity increases

Engineering Contradiction:
ImproveISI correction capabilityVSAvoidequalizer complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The equalizer is segmented into multiple independent DFFE stages, each handling specific ISI components. The first stage corrects precursor ISI while subsequent stages correct postcursor ISI, allowing selective noise management for different ISI types without uniform noise amplification across all correction functions.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The multi-stage DFFE architecture allows dynamic adaptation where each stage can be independently optimized and adjusted. This enables flexible complexity management by activating only the necessary number of stages based on channel conditions, rather than requiring all taps to be always active.

Inventive Principle:
Principle #15Dynamics

4Device complexity

If CDR and equalization are coupled, then adaptation is simplified, but CDR locking point becomes sub-optimal and sensitivity to transmitter settings increases

Engineering Contradiction:
Improveadaptation couplingVSAvoidCDR locking point stability
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The equalizer is segmented into multiple independent DFFE stages, each handling specific ISI components. The first stage corrects precursor ISI while subsequent stages correct postcursor ISI, allowing selective noise management for different ISI types without uniform noise amplification across all correction functions.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The multi-stage DFFE acts as an intermediary between the channel and the CDR, providing progressive ISI correction that prepares the signal for optimal CDR locking. By decoupling the adaptation processes while maintaining signal conditioning, the DFFE enables CDR to achieve optimal locking points without being constrained by simplified coupled adaptation.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS10911272B2Multi-tap decision feed-forward equalizer with precursor and postcursor taps
Publication Date: 2021.02.02 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US10911272B2 patent drawing
  • US10911272B2 patent drawing
  • US10911272B2 patent drawing

AI summary

A multi-tap Differential Feedforward Equalizer (DFFE) configuration with both precursor and postcursor taps is provided. The DFFE has reduced noise and/or crosstalk characteristics when compared to a Feedforward Equalizer (FFE) since DFFE uses decision outputs of slicers as inputs to a finite impulse response (FIR) unlike FFE which uses actual analog signal inputs. The digital outputs of the tentative decision slicers are multiplied with tap coefficients to reduce noise. Further, since digital outputs are used as the multiplier inputs, the multipliers effectively work as adders which are less complex to implement. The decisions at the outputs of the tentative decision slicers are tentative and are used in a FIR filter to equalize the signal; the equalized signal may be provided as input to the next stage slicers. The bit-error-rate (BER) of the final stage decisions are lower or better than the BER of the previous stage tentative decisions.