Multi-Thickness Conductor Layer for Electronics Package
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Solution Overview
Problem
Existing semiconductor device packaging technologies face challenges in miniaturization due to the need for varying current carrying and routing density requirements across different types of semiconductor devices, leading to increased package thickness, complexity, and reduced design flexibility and cost efficiency.
Innovation Solution
A multi-thickness conductor layer with varying thicknesses is integrated into a common horizontal plane within the electronics package, allowing for localized high current carrying and high density interconnection capabilities, enabling closer proximity of disparate semiconductor devices and reducing conductor length between components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple routing layers with varying thicknesses are used to meet different current carrying and routing density requirements, then the electrical performance and current carrying capability are improved, but the package thickness and structural complexity increase
Solution Approach 1:
The patent implements a multi-thickness conductor layer where different regions have different thicknesses to satisfy local current carrying and routing density requirements. Thicker regions provide high current carrying capability for power devices, while thinner regions provide high routing density for digital devices, all within a single horizontal plane rather than multiple stacked layers.
Solution Approach 2:
The patent transitions from using multiple vertical routing layers (z-dimension) to using a single horizontal plane with varying thickness (x-y plane with thickness variation). This dimensional reorganization allows different conductor thicknesses to coexist in one plane, reducing overall package thickness while maintaining the ability to satisfy different electrical requirements.
2Reliability
If multiple routing layers are used to accommodate different current carrying and routing density requirements, then the electrical performance is improved, but the conductor structure becomes long and complex
Solution Approach 1:
The conductor layer is designed with locally varied thicknesses where thicker sections are positioned near power devices to handle high currents, and thinner sections are positioned near digital devices to achieve high routing density. This local differentiation reduces the need for long conductors traversing multiple layers, shortening the overall conductor path while maintaining electrical performance.
3Adaptability or versatility
If individually packaged components are mounted on a multi-layer PCB, then different types of semiconductor devices can be integrated, but the overall package size and thickness increase
Solution Approach 1:
The patent merges the functions of multiple routing layers into a single multi-thickness conductor layer. By combining high current carrying capability and high routing density requirements into one horizontal plane with locally varied thickness, the design reduces the number of discrete layers needed, thereby miniaturizing the overall package while maintaining the ability to integrate different device types.
Data Source
AI summary
An electronics package includes an insulating substrate and electrical components coupled to a first surface of the insulating substrate. A multi-thickness conductor layer is formed on a second surface of the insulating substrate opposite the first surface. The multi-thickness conductor layer extends through vias in the insulating substrate to connect with contact pads of the electrical components. The multi-thickness conductor layer has a first thickness in a region proximate the first electrical component and a second thickness in a region proximate the second electrical component, the first thickness greater than the second thickness. The electronics package also includes a first redistribution layer having a conductor layer formed atop a portion of the multi-thickness conductor layer having the second thickness. A top surface of the conductor layer is co-planar with or substantially co-planar with a top surface of a portion of the multi-thickness conductor layer having the first thickness.