Multi-Thickness Gate Dielectric for HVMOS Reliability
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Solution Overview
Problem
High voltage metal-oxide-semiconductor (HVMOS) devices face reliability issues due to high gate current, which can be exacerbated by attempts to reduce it, such as increased turn-on resistance.
Innovation Solution
A semiconductor device with a gate dielectric having multiple thicknesses, where a second thickness is greater than the first, is fabricated using a method involving a semiconductor substrate with a buried layer and high voltage wells, and a gate structure with a gate dielectric layer and electrode, to reduce gate current and enhance reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the drift region doping is reduced to reduce gate current, then gate current is reduced, but turn-on resistance increases
Solution Approach 1:
The gate dielectric is designed with non-uniform thickness, having a first thickness in the first region and a second thickness in the second region. This local variation in dielectric thickness allows different regions to have different electrical characteristics, enabling the device to reduce gate current while maintaining appropriate turn-on resistance through spatially differentiated properties
Data Source
AI summary
A semiconductor device is provided that, in an embodiment, is in the form of a high voltage MOS (HVMOS) device. The device includes a semiconductor substrate and a gate structure formed on the semiconductor substrate. The gate structure includes a gate dielectric which has a first portion with a first thickness and a second portion with a second thickness. The second thickness is greater than the first thickness. A gate electrode is disposed on the first and second portion. In an embodiment, a drift region underlies the second portion of the gate dielectric. A method of fabricating the same is also provided.