Multi-thickness Gate Insulator for SOA and On-Resistance Trade-off
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Solution Overview
Problem
Semiconductor devices with high gain have a limited safe operating area (SOA), which is compromised by increased on-resistance when attempting to reduce gain through thicker gate oxides, impacting performance in various applications.
Innovation Solution
Incorporating a varied gate-channel structure with differing gate oxide thicknesses and doping levels along the channel length to manage gain and SOA performance, specifically by having sections with thicker gate oxides or varying doping levels to reduce gain and enhance SOA during saturation mode.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the gate oxide thickness is increased to reduce gain, then the safe operating area (SOA) performance is improved, but the on-resistance increases which compromises device performance
Solution Approach 1:
The patent applies local quality by implementing different gate oxide thicknesses in different regions of the device. Specifically, the gate oxide has a first thickness in a first region and a second thickness in a second region, allowing each region to be optimized for its specific function - one region for gain control and another for maintaining low on-resistance
Solution Approach 2:
The gate oxide structure is segmented into multiple regions with different thicknesses. This segmentation allows the device to achieve both high SOA performance (through thicker oxide regions that reduce gain) and low on-resistance (through thinner oxide regions), resolving the technical contradiction by dividing the gate oxide into functionally distinct segments
2Manufacturing precision
If the gate oxide thickness is decreased to maintain low on-resistance, then the device performance is improved, but the gain increases which reduces the safe operating area (SOA)
Solution Approach 1:
Different regions of the gate oxide are assigned different thicknesses to locally optimize for either low on-resistance or reduced gain, with thinner oxide in regions requiring low resistance and thicker oxide in regions requiring gain control
Solution Approach 2:
The gate oxide is divided into multiple segments with varying thicknesses, enabling simultaneous achievement of low on-resistance (through thin oxide segments) and high SOA performance (through thick oxide segments that reduce gain)
Data Source
AI summary
Systems and methods of the disclosed embodiments include an electronic device that has a gate electrode for supplying a gate voltage, a source, a drain, and a channel doped to enable a current to flow from the drain to the source when a voltage is applied to the gate electrode. The electronic device may also include a gate insulator between the channel and the gate electrode. The gate insulator may include a first gate insulator section including a first thickness, and a second gate insulator section including a second thickness that is less than the first thickness. The gate insulator sections thereby improve the safe operating area by enabling the current to flow through the second gate insulator section at a lower voltage than the first gate insulator section.