Multi-Thickness Nanowire Transistor Structure for Bottleneck Reduction
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Solution Overview
Problem
Existing semiconductor devices face challenges in enhancing the operating characteristics and reducing the bottle neck phenomenon in nanowire transistors, particularly in achieving faster operating speeds and improved integration density.
Innovation Solution
The proposed solution involves a semiconductor device design with a nanowire transistor that includes a first section with a first thickness and a second section with a second thickness, where the second section is between the first section and at least one of the source or drain. This design allows for a channel to be formed when a voltage is applied to the gate electrode, enhancing the transistor's performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a nanowire transistor with uniform thickness is used, then the manufacturing process is simple, but the operating speed is limited due to bottle neck phenomenon
Solution Approach 1:
The nanowire is designed with non-uniform thickness, featuring a first section with first thickness and a second section with second thickness. This local variation in dimensions allows optimization of carrier transport in different regions, reducing the bottle neck phenomenon and improving operating speed without requiring complete structural redesign.
Solution Approach 2:
The nanowire channel is divided into multiple sections with different thicknesses. The first section and second section are formed as distinct segments with different cross-sectional dimensions, allowing independent optimization of each region's electrical characteristics to enhance overall device performance.
2Reliability
If the nanowire thickness is increased to reduce bottle neck phenomenon, then the operating characteristics improve, but the integration density decreases
Solution Approach 1:
Instead of uniformly increasing nanowire thickness throughout the entire channel, the invention applies thickness variation locally - the second section has different thickness than the first section. This allows improvement of operating characteristics in specific regions while maintaining compact overall dimensions for high integration density.
Solution Approach 2:
The invention transitions from considering only the cross-sectional dimension to incorporating the longitudinal dimension variation. By varying thickness along the channel length (different first and second sections), the design optimizes carrier transport without proportionally increasing the device footprint, thereby maintaining integration density.
3Productivity
If a multi-thickness nanowire structure is implemented, then the bottle neck phenomenon is reduced, but the manufacturing precision requirements increase
Solution Approach 1:
The manufacturing process is segmented into distinct stages for forming the first section and second section of the nanowire. Each section can be formed using separate deposition or growth steps, allowing independent control and relaxation of precision requirements for each segment rather than requiring uniform high precision throughout.
Solution Approach 2:
The invention utilizes changes in deposition parameters or growth conditions to achieve different thicknesses in different sections. By modifying process parameters (such as deposition rate, temperature, or precursor flow) between forming the first and second sections, the desired thickness variation is achieved with standard manufacturing precision capabilities.
Data Source
AI summary
A semiconductor device includes a drain, a source, a gate electrode, and a nanowire between the source and drain. The nanowire has a first section with a first thickness and a second section with a second thickness greater than the first thickness. The second section is between the first section and at least one of the source or drain. The first nanowire includes a channel when a voltage is applied to the gate electrode.