Multi-Thickness PIN Diode Structure for Frequency Response Control
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Solution Overview
Problem
Current design and fabrication techniques for planar PIN diodes limit the types of diode structures that can be realized across a silicon wafer, as they result in all PIN diodes having the same intrinsic region thickness, which is inadequate for achieving control over desired frequency ranges and other operating characteristics in high-frequency circuit functions.
Innovation Solution
A monolithic, vertical, planar semiconductor structure with multiple PIN diodes having different intrinsic regions of varying thicknesses is developed, where multiple P-type or N-type regions are formed to different depths within the intrinsic layer, allowing for the creation of diodes with distinct intrinsic region thicknesses, which can be integrated with other components like capacitors and inductors in a monolithic circuit format.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If traditional vertical layer growth or deposition techniques are used to fabricate PIN diodes, then the fabrication process is simple and straightforward, but all PIN diodes end up with the same intrinsic region thickness, limiting control over frequency ranges and operating characteristics
Solution Approach 1:
The patent segments the single intrinsic layer into multiple regions with different thicknesses by forming openings at different locations and depths. Each opening exposes a different thickness of the intrinsic layer, allowing multiple PIN diodes with different characteristics to be fabricated on the same substrate. This segmentation enables control over frequency ranges and operating characteristics while maintaining a relatively simple fabrication process.
Solution Approach 2:
The patent applies local quality by creating regions of different intrinsic layer thicknesses at specific locations on the substrate. By controlling the depth and position of openings, each PIN diode region receives a tailored thickness of intrinsic material, providing locally optimized electrical characteristics for different frequency ranges and applications.
2Manufacturing precision
If multiple PIN diodes with different intrinsic region thicknesses are fabricated on the same wafer, then frequency response control is improved, but the fabrication process becomes more complex
Solution Approach 1:
The patent performs preliminary action by forming all openings in the dielectric layer before forming the P-type regions. This sequence allows precise control over the thickness of the intrinsic layer exposed at each opening, as the openings are created to specific depths and positions. The P-type regions are then formed to contact the intrinsic layer at these pre-determined locations, ensuring accurate thickness control for each PIN diode.
Solution Approach 2:
The patent utilizes the vertical dimension by forming openings of different depths into the intrinsic layer. This dimensional approach allows multiple PIN diodes with different intrinsic region thicknesses to be created on the same wafer surface, enabling precise thickness control without requiring separate wafers or complex post-fabrication processing.
3Productivity
If all PIN diodes have the same intrinsic region thickness, then the fabrication process is consistent and simple, but the device cannot achieve control over desired frequency ranges
Solution Approach 1:
The patent achieves universality by creating a multi-functional substrate that can support multiple PIN diodes with different frequency characteristics on the same wafer. The single intrinsic layer serves multiple functions by being accessed at different depths through openings, allowing one fabrication process to produce devices for different frequency ranges, thereby improving both productivity and adaptability.
Solution Approach 2:
The patent segments the uniform intrinsic layer into effectively different thickness regions by creating openings at controlled depths. This segmentation allows a single fabrication run to produce multiple PIN diodes with different electrical characteristics, maintaining high productivity while enabling frequency range control across different device regions.
Data Source
AI summary
A monolithic, vertical, planar semiconductor structure with a number diodes having different intrinsic regions is described. The diodes have intrinsic regions of different thicknesses as compared to each other. In one example, the semiconductor structure includes an N-type silicon substrate, an intrinsic layer formed on the N-type silicon substrate, and a dielectric layer formed on the intrinsic layer. A number of openings are formed in the dielectric layer. Multiple anodes are sequentially formed into the intrinsic layer through the openings formed in the dielectric layer. For example, a first P-type region is formed through a first one the openings to a first depth into the intrinsic layer, and a second P-type region is formed through a second one of the openings to a second depth into the intrinsic layer. Additional P-type regions can be formed to other depths.