Multi-thread Image Scaler for ADAS Memory Reduction
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Solution Overview
Problem
Current image scaling methods in computer vision systems for advanced driver assistance systems (ADAS) are inefficient due to high memory and silicon area requirements, making them unsuitable for embedded applications.
Innovation Solution
A multi-thread image scaler with multiple shared scalers that perform vertical scaling followed by horizontal scaling, eliminating the need for line buffers and allowing for unified polyphase filtering, dual precision modes, and efficient sharing of coefficient sets to generate image pyramids with arbitrary scaling ratios.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If current image scaling methods are used to generate image pyramids, then image scaling functionality is achieved, but memory requirements and silicon area requirements increase significantly
Solution Approach 1:
The patent merges multiple scaling operations into a unified polyphase filtering architecture. Instead of implementing separate scaling algorithms that each require dedicated memory, the invention combines them into a single filter bank structure where coefficients are shared across different scaling operations. This merging eliminates redundant memory storage while preserving all scaling functionalities.
Solution Approach 2:
The polyphase filter bank is designed as a universal structure that can perform multiple scaling operations (different scaling ratios, image pyramid generation, etc.) using the same hardware resources. The filter coefficients and architecture serve multiple purposes, allowing the system to achieve various scaling functions without requiring separate dedicated memory for each operation, thus reducing overall memory requirements.
2Reliability
If current image scaling methods are used to generate image pyramids, then image scaling functionality is achieved, but silicon area requirements increase significantly
Solution Approach 1:
The patent merges multiple scaling operations into a unified polyphase filtering architecture. Instead of implementing separate scaling algorithms that each require dedicated memory, the invention combines them into a single filter bank structure where coefficients are shared across different scaling operations. This merging eliminates redundant memory storage while preserving all scaling functionalities.
Solution Approach 2:
The invention changes the fundamental parameter representation by using polyphase filter coefficients that can be configured for different scaling ratios. By parameterizing the filter bank to accept different coefficient sets and configuration parameters, the same hardware structure can adapt to various scaling requirements without requiring additional silicon area for each configuration.
3Adaptability or versatility
If multiple independent scalers are used to achieve arbitrary scaling ratios, then scaling flexibility is improved, but device complexity and memory requirements increase
Solution Approach 1:
The polyphase filter bank is designed as a universal structure that can perform multiple scaling operations (different scaling ratios, image pyramid generation, etc.) using the same hardware resources. The filter coefficients and architecture serve multiple purposes, allowing the system to achieve various scaling functions without requiring separate dedicated memory for each operation, thus reducing overall memory requirements.
Solution Approach 2:
The scaler architecture is made dynamic and reconfigurable through the polyphase filter bank structure. Instead of fixed independent scalers, the system can dynamically configure the filter coefficients and phase connections to achieve different scaling ratios on-demand. This dynamic reconfiguration capability provides scaling flexibility without requiring multiple permanent scaler structures.
Data Source
AI summary
An apparatus for scaling images is provided that includes at least two input ports, a scaling component coupled to the at least two input ports, the scaling component including a plurality of scalers, the scaling component configurable to map any scaler to any input port of the at least two input ports and configurable to map more than one scaler to any input port, and a memory coupled to the at least two input ports and to outputs of the plurality of scalers, the memory configured to store image data for each input port and scaled image data output by the plurality of scalers.