Multi-thread Processor Dynamic CPU Bandwidth Allocation
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Solution Overview
Problem
Multi-threaded processors face challenges in dynamically allocating CPU bandwidth and handling interrupts efficiently, particularly in scenarios where unequal allocation is needed and interrupt handling is delayed due to sequential processing.
Innovation Solution
A multi-thread superscalar processor with a re-programmable thread map register that dynamically allocates CPU cycles to each thread and provides separate interrupt handling for each thread, allowing for granular control of thread execution and concurrent processing of multiple protocols.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a multi-threaded processor uses sequential interrupt handling where new interrupts are disabled during previous interrupt processing, then interrupt handling completeness is ensured, but interrupt recognition timeliness deteriorates
Solution Approach 1:
The patent segments the interrupt handling process by assigning separate dedicated threads for different interrupt sources. Each thread independently handles its specific interrupt type without blocking others, allowing parallel interrupt processing. This segmentation enables timely recognition of new interrupts while maintaining complete handling of previous interrupts through independent thread execution.
2Ease of operation
If CPU bandwidth is allocated equally to multiple threads, then thread fairness is maintained, but dynamic allocation flexibility deteriorates
Solution Approach 1:
The patent implements dynamic CPU bandwidth allocation by allowing the thread map register to be re-programmable. This enables the system to dynamically adjust the number of threads and their corresponding CPU cycle allocations based on real-time protocol activity levels. Threads can be added or removed, and their allocation percentages can be changed without system reconfiguration, providing both fairness and adaptability.
Solution Approach 2:
The patent changes the allocation parameter from fixed equal distribution to variable percentage allocation. The thread map register allows programming of different thread counts and CPU cycle percentages for each thread. This parameter change enables the system to adapt CPU resources dynamically based on protocol requirements while maintaining fairness through configurable allocation policies.
3Stability of the object's composition
If a fixed thread allocation is used, then system stability is maintained, but dynamic thread addition or removal capability deteriorates
Solution Approach 1:
The patent transforms the static thread allocation model into a dynamic one through the re-programmable thread map register. This allows the number of active threads and their allocation percentages to be changed at runtime based on protocol activity. The system can add threads when protocol activity increases and remove threads when activity decreases, maintaining stability through controlled dynamic reconfiguration rather than fixed allocation.
Data Source
AI summary
A multi-thread communication system has several communications processors operative over a single interface for transmitting and receiving packets. The multi-thread communications processor is operative to sequentially handle multiple thread processes for each communications processor on a cycle by cycle basis according to a thread map register which determines the order of execution and how many cycles of a particular thread occur during a canonical interval.