Multi-thread Processor with Mode Register for Thread Allocation
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Solution Overview
Problem
Existing processors are inefficient in processing various vectorized application codes, particularly in artificial intelligence systems that require rapid processing of vast amounts of data, such as image data for real-time applications in driver assistance systems and increasing digital TV and smartphone resolutions.
Innovation Solution
A multi-thread processor architecture that concurrently processes threads of different sizes by utilizing a mode register to allocate threads to functional units, including scalar and vector functional units, and a controller to manage thread processing, allowing for efficient execution of programs with reconfigurable architecture supporting both coarse-grained array and very long instruction word modes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a data parallelization processor is used to rapidly process increased amounts of data, then processing speed is improved, but efficiency in processing certain application code deteriorates
Solution Approach 1:
The processor employs dynamic thread configuration where the number of threads and their widths can be adjusted in real-time based on application requirements. The functional units can be reconfigured between coarse-grained array mode and very long instruction word mode, allowing the system to adapt its processing architecture dynamically to match different computational workloads and code types, thereby maintaining both high speed and high efficiency across diverse applications
Solution Approach 2:
The processor integrates multiple processing modes within a single architecture, supporting both data parallelization operations and multi-threaded vectorized application code execution. By incorporating scalar and vector functional units that can operate in different configurations, the system achieves universal applicability across various computational tasks, from simple data processing to complex AI algorithms
2Speed
If the processor architecture is simplified for fast processing, then processing speed is improved, but the ability to handle complex AI algorithms and various thread sizes deteriorates
Solution Approach 1:
The processor divides its functional units into distinct scalar and vector units, each optimized for specific types of operations. This segmentation allows independent optimization of each unit for speed while maintaining the capability to handle complex algorithms through coordinated operation of multiple units. The functional units can be selectively activated based on the computational requirements of the current task
3Productivity
If multiple threads of different sizes are processed concurrently, then processor efficiency is improved, but control and management complexity increases
Solution Approach 1:
The controller dynamically adjusts thread configuration parameters including the number of concurrent threads and their respective widths based on the current computational workload. This dynamic adaptation allows efficient processor utilization across different scenarios without requiring complex static management structures, as the system automatically optimizes its thread configuration to match application demands
Data Source
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AI summary
A multi-thread processor and a method of controlling a multi-thread processor are provided. The multi-thread processor includes at least one functional unit; a mode register; and a controller configured to control the mode register to store thread mode information corresponding to a task to be processed among a plurality of thread modes, wherein the plurality of thread modes are divided based on a size and a number of at least one thread that is concurrently processed in one of the at least one functional unit, allocate at least one thread included in the task to the at least one functional unit based on the thread mode information stored in the mode register and control the at least one functional unit to process the at least one thread.