Multi-thread Processor Architecture for Split Instruction Execution
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Solution Overview
Problem
Current microprocessors face challenges in efficiently executing multiple instructions on smaller data widths while maintaining high throughput and low power consumption, particularly in applications like IoT and machine learning, where traditional 32-bit architectures are inefficient for smaller bit operations.
Innovation Solution
A pipelined multi-thread microprocessor architecture that supports both thread mode and micro-thread mode operations, utilizing a thread_id generator, per-thread register files, and pipeline stages for simultaneous execution of instructions, allowing for execution of multiple instructions on smaller data widths without increasing complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional 32-bit architecture is used for smaller bit operations, then computational precision is maintained, but processing efficiency and power consumption deteriorate
Solution Approach 1:
The processor architecture segments the execution units into multiple lanes (e.g., 4 lanes of 8-bit operations) within a single core, allowing parallel execution of smaller operations. This segmentation enables efficient processing of small data widths by dedicating specific execution resources to them, avoiding the energy waste of using full 32-bit units for small operations.
Solution Approach 2:
The patent introduces a new dimension of parallelism by implementing multiple execution lanes that can operate simultaneously on different data elements. Instead of sequentially processing small operations on a single 32-bit unit, the architecture adds lateral parallelism through multiple lanes, achieving higher throughput for small operations without increasing clock frequency or voltage.
2Productivity
If multiple processor cores are used to increase throughput, then computational power is improved, but device complexity and silicon area increase
Solution Approach 1:
The patent merges multiple execution capabilities into a single processor core by implementing superscalar architecture with multiple execution lanes and out-of-order execution. This consolidation allows the core to handle multiple instructions simultaneously through resource sharing and dynamic scheduling, achieving multi-core-like throughput without the physical multiplication of cores and their associated complexity.
Solution Approach 2:
The architecture employs dynamic resource allocation and out-of-order execution to adaptively schedule instructions across multiple execution lanes. The dynamic instruction dispatch and resource management allow the single core to flexibly handle varying workloads, achieving high throughput without the static complexity of multiple dedicated cores.
3Device complexity
If in-order execution architecture is used, then simplicity and flexibility are maintained, but instruction throughput is limited to 1 IPC
Solution Approach 1:
The patent implements out-of-order execution by performing preliminary actions: instructions are dispatched early to execution units before all dependencies are resolved, and execution resources are pre-configured to handle multiple instruction types. This preliminary preparation allows instructions to execute as soon as their operands are ready, breaking the strict in-order bottleneck while maintaining manageable complexity through hardware buffering and dependency tracking.
Solution Approach 2:
The architecture changes the execution parameter from sequential (in-order) to parallel (out-of-order) by implementing multiple execution lanes with independent instruction pointers and status flags. This parameter change enables the processor to execute multiple instructions per cycle by altering the fundamental execution flow, achieving higher IPC without completely redesigning the control logic.
4Device complexity
If thread mode executes single instruction at granularity of data word width, then simplicity is maintained, but execution speed for multiple operations deteriorates
Solution Approach 1:
The processor segments the instruction execution into multiple parallel lanes, where each lane can independently execute operations on different data elements simultaneously. This segmentation allows the simple thread mode to achieve higher effective execution speed by dividing the work across multiple narrow lanes rather than using a single wide lane sequentially.
Data Source
AI summary
A superscalar processor has a thread mode of operation for supporting multiple instruction execution threads which are full data path wide instructions, and a micro-thread mode of operation where each thread supports two micro-threads which independently execute instructions. An executed instruction sets a micro-thread mode and an executed instruction sets the thread mode.