Multi-threaded Accelerator Integration in CPU Cores
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Solution Overview
Problem
Traditional co-processors in computing systems are viewed as separate entities from CPU cores, leading to large latencies and inefficient communication, which limits their use to coarse-grained tasks, whereas there is a need for finer-grained acceleration integration.
Innovation Solution
Designing accelerators as tightly coupled functional units within the CPU core, allowing them to operate within the same memory space and enabling invocation of multi-threaded execution units that parallelize tasks, reducing the need for expensive driver calls and enhancing fine-grained task execution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional co-processors are used as separate devices external to CPU cores, then device isolation and dedicated functionality are achieved, but large latencies and inefficient communication occur
Solution Approach 1:
The patent merges the accelerator with the CPU core by placing it in the same address space and allowing direct invocation without driver software. The accelerator is integrated into the processing core structure, enabling tasks to be invoked directly from CPU threads without the overhead of device driver communication, thereby reducing latency while maintaining dedicated acceleration functionality.
2Reliability
If traditional co-processors are accessed through device driver software, then separate device isolation is maintained, but significant communication resources are expended
Solution Approach 1:
The accelerator is combined with the CPU core into a unified processing unit that shares the same address space. This integration eliminates the need for device driver software and special communication protocols, allowing direct task invocation from CPU threads. The merging reduces communication overhead and energy consumption while preserving functional isolation through software-controlled task allocation.
3Adaptability or versatility
If traditional co-processors operate outside the CPU memory space, then separate address translation schemes are used, but integration and coordination with CPU threads are reduced
Solution Approach 1:
The accelerator operates within the same address space as the CPU core, sharing the virtual-to-physical address translation mechanism. This integration allows CPU threads to directly invoke accelerator tasks using standard memory addressing without requiring separate address translation schemes or special communication protocols, thereby improving ease of operation and coordination.
4Productivity
If coarse-grained task invocation is used on traditional co-processors, then large blocks of data per task are processed, but fine-grained task execution is limited
Solution Approach 1:
The patent enables fine-grained task invocation by allowing individual CPU threads to directly invoke small, specific tasks on the accelerator without requiring large data blocks. The segmentation of functionality allows the accelerator to handle both fine-grained individual tasks and coarse-grained bulk processing, providing versatility in task granularity while maintaining productivity.
Data Source
AI summary
A processor is described having logic circuitry of a general purpose CPU core to save multiple copies of context of a thread of the general purpose CPU core to prepare multiple micro-threads of a multi-threaded accelerator for execution to accelerate operations for the thread through parallel execution of the micro-threads.