Multi-Threaded DMA Request Handling During Synchronization Waits

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Solution Overview

Problem

Integrated circuit devices experience significant performance drains due to idle time of the DMA engine during wait periods required for fulfilling data movement requests, which are necessitated by out-of-order reads/writes, leading to undesirable latency in servicing data requests.

Innovation Solution

Implementing a DMA engine that serves multiple data movement request queues through multiple threads, allowing it to perform data movement operations during wait periods associated with other tasks, thereby reducing idle time and enhancing performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If a single-threaded DMA engine services data movement requests sequentially, then the system structure is simple, but the DMA engine experiences significant idle time during wait periods required for out-of-order reads/writes

Engineering Contradiction:
ImproveDMA engine productivityVSAvoididle time
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The patent divides the single DMA engine into multiple threads (first thread, second thread, etc.), where each thread services a separate data movement request queue. This segmentation allows different data movement operations to execute in parallel, eliminating idle time while maintaining simple per-thread structures.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent implements dynamic thread scheduling where the DMA engine can switch between threads based on availability of data movement requests and completion of wait periods. This dynamic approach optimizes productivity by ensuring continuous operation without idle periods.

Inventive Principle:
Principle #15Dynamics

2Ease of operation

If the DMA engine performs data movement operations sequentially in a single thread, then the control logic is simple, but latency in servicing data requests increases due to wait periods

Engineering Contradiction:
Improvecontrol logic simplicityVSAvoidlatency
Core Design Contradiction:
Ease of operationVSLoss of time

Solution Approach 1:

The control logic is segmented into independent thread-level controllers, each managing its own data movement request queue. This segmentation reduces overall latency by allowing parallel processing while keeping each individual thread's control logic simple and manageable.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent transitions from single-thread sequential execution to multi-thread parallel execution, adding the dimension of temporal parallelism. This reduces latency by performing data movement operations simultaneously across multiple threads rather than sequentially.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Reliability

If the DMA engine waits for sync operations to complete before servicing new requests, then data integrity is maintained, but performance is reduced due to sequential processing

Engineering Contradiction:
Improvedata integrityVSAvoidDMA engine performance
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent segments data movement requests into separate queues associated with different threads, allowing independent progression of each thread. Each thread maintains data integrity for its own requests while other threads can simultaneously service different requests, improving overall performance without compromising reliability.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent implements preliminary actions by pre-allocating threads and queues before data movement operations begin. Threads can be assigned to different request queues in advance, enabling parallel execution while maintaining synchronization barriers that ensure data integrity is preserved.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS12436906B1Multi-threaded data movement request handling
Publication Date: 2025.10.07 AMAZON TECH INC
  • US12436906B1 patent drawing
  • US12436906B1 patent drawing
  • US12436906B1 patent drawing

AI summary

Multi-threaded data movement request handling techniques are disclosed. The techniques can include performing, by a direct memory access (DMA) engine, one or more data movement operations associated with a data movement phase of a first data movement task, initiating a data movement phase of a second data movement task during a wait period for the sync phase of the first data movement task, initiating the sync phase of the first data movement task following expiration of the wait period for the sync phase of the first data movement task, and performing a sync operation associated with the sync phase of the first data movement task.