Multi-threaded Processor and Hardware Block Interface for Packet Processing
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Solution Overview
Problem
Existing processing devices for applications like packet processing and digital signal processing are limited by inflexible pipeline architectures, which restrict speed and efficiency due to sequential operation and inability to handle varying data types effectively.
Innovation Solution
A data processing apparatus combining multi-threaded processors with hardware blocks, allowing for flexible processing sequences where software controls high-level tasks and dedicated hardware handles computationally intensive events, with interface circuitry for coordinated data transfer and optional order enforcement.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If traditional pipelined processing devices are used, then sequential processing is guaranteed, but processing speed is limited by the slowest stage and flexibility is reduced
Solution Approach 1:
The patent implements dynamic thread scheduling where the processor can switch between multiple threads based on packet processing requirements. Each thread can be dynamically assigned to different hardware blocks for different processing stages, allowing the system to adapt to varying data types and processing needs while maintaining high throughput by executing multiple packets simultaneously at different stages.
2Reliability
If sequential pipeline processing is used, then each unit of data passes through each stage properly, but processing efficiency decreases due to inability to handle varying data types
Solution Approach 1:
The patent divides the packet processing function into separate threads, where each thread corresponds to a specific processing stage or hardware block. This segmentation allows independent execution of different processing operations simultaneously. The scheduler manages these threads to ensure correct processing sequence while enabling parallel execution, thereby maintaining both reliability and efficiency.
Solution Approach 2:
The system pre-loads multiple packets into different processing stages before actual processing begins. The scheduler can identify idle threads and assign ready packets to appropriate hardware blocks in advance, reducing waiting time and improving overall processing efficiency while ensuring correct execution through predefined processing sequences.
3Productivity
If dedicated hardware blocks are added for computationally intensive events, then processing performance improves, but device complexity increases
Solution Approach 1:
The patent designs a universal hardware block interface that can be configured to perform different computationally intensive operations based on software control. The same hardware block structure can be reused for different processing tasks by loading different operation data, reducing the need for multiple specialized hardware blocks and thereby limiting the increase in device complexity while maintaining high processing performance.
Data Source
AI summary
In the provided architecture, one or more multi-threaded processors may be combined with hardware blocks. The resulting combination allows for data packets to undergo a processing sequence having the flexibility of software programmability with the high-performance of dedicated hardware. For example, a multi-threaded processor can control the high-level tasks of a processing sequence, while the computationally intensive events (e.g., signal processing filters, matrix operations, etc.) are handled by dedicated hardware blocks.