Multi-threaded Processor Trace Messages with Virtual Core ID

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Solution Overview

Problem

The Nexus standard for debugging processors is not applicable to high-end processors with multi-threading capability, as it fails to differentiate between threads, making it impossible to debug processors employing multi-threading architectures effectively.

Innovation Solution

Incorporating a virtual core identification (VCID) into trace messages to identify associated threads, allowing debug tools to correctly reconstruct program flows and retrieve memory data references in multi-threaded processors, and extending the Nexus standard to support simultaneous multi-threading (SMT) and thread switch multi-threading (TMT) architectures with separate or common trace front-ends.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If the Nexus standard is used for debugging processors, then basic debug functions are provided, but it cannot differentiate between threads in multi-threaded processors

Engineering Contradiction:

Improvethread differentiation capabilityVSAvoidthread identification information

Core Design Contradiction:

Adaptability or versatilityVSLoss of information

Solution Approach 1:

The trace message format is segmented to include a dedicated thread identification field that separately carries thread ID information, allowing the debug system to distinguish between different threads while maintaining compatibility with the existing Nexus standard structure

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

A thread identification field acts as an intermediary element in the trace message, bridging the gap between the existing Nexus standard and multi-threaded processing requirements, enabling thread differentiation without fundamentally altering the standard's core functionality

Inventive Principle:

Principle #24Intermediary (Mediator)

2Measurement precision

If multiple trace front-ends are implemented for each thread, then thread-specific tracing is enabled, but device complexity increases

Engineering Contradiction:

Improvethread-specific trace accuracyVSAvoidtrace front-end architecture

Core Design Contradiction:

Measurement precisionVSDevice complexity

Solution Approach 1:

Multiple trace front-ends are merged into a single shared trace front-end that processes traces from all threads, reducing hardware complexity while maintaining thread-specific tracing capability through the inclusion of thread identification information in the trace messages

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The single trace front-end is designed with universal functionality to handle traces from multiple threads simultaneously, eliminating the need for dedicated trace front-ends for each thread while preserving thread-specific measurement precision

Inventive Principle:

Principle #6Universality (Multi-functionality)

3Adaptability or versatility

If thread identification is added to trace messages, then thread correlation is enabled, but message format complexity increases

Engineering Contradiction:

Improvethread correlation capabilityVSAvoidmessage format structure

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

Thread identification information is extracted as a separate, dedicated field in the trace message format, clearly delineated from other message components, which simplifies the overall structure by providing a明确的 boundary for thread-related data

Inventive Principle:

Principle #2Taking out (Extraction)

Data Source

PatentUS9195462B2Techniques for tracing processes in a multi-threaded processor

Publication Date: 2015.11.24 VLSI TECHNOLOGY LLC

AI summary

A technique for tracing processes executing in a multi-threaded processor includes forming a trace message that includes a virtual core identification (VCID) that identifies an associated thread. The trace message, including the VCID, is then transmitted to a debug tool.