Multi-threshold FET via Local Implantation
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Solution Overview
Problem
Current methods for fabricating multi-threshold voltage field effect transistors (FETs) face challenges such as mobility degradation, junction leakage, and increased cost due to heavy implantation processes and the need for multiple masks, which are particularly problematic in thin-body FET settings like FinFETs and nanowire FETs.
Innovation Solution
A method to implement multiple threshold voltage FETs using only two metal gates and two threshold voltage implants, reducing impurity scattering and trap generation, thereby enhancing carrier mobility and reducing gate-induced drain leakage and band-to-band tunneling currents, while allowing for the formation of eight transistors with different threshold voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If heavy implantation processes are used to achieve higher threshold voltage devices, then threshold voltage is improved, but mobility degradation and junction leakage current increase
Solution Approach 1:
The patent applies different implantation doses to different regions of the channel. Specifically, it uses a first implantation dose for a first portion of the channel and a second implantation dose for a second portion of the channel, where the doses differ. This local differentiation allows achieving desired threshold voltage characteristics without requiring heavy uniform implantation throughout the entire channel, thereby reducing mobility degradation and junction leakage current while still achieving the required threshold voltage.
Solution Approach 2:
The patent changes the implantation dose parameter across different portions of the channel. By varying the implantation dose (using different doses for different channel portions) rather than applying a uniform heavy dose, the method achieves the required threshold voltage adjustment while minimizing the harmful effects of heavy implantation such as mobility degradation and increased leakage current.
2Manufacturing precision
If separate masks are used for each desired threshold voltage, then different threshold voltage devices are achieved, but manufacturing cost increases
Solution Approach 1:
The patent uses a single mask pattern that simultaneously defines multiple device regions requiring different threshold voltages. By designing the mask to expose different portions of different devices in a single step, the method achieves multi-threshold voltage device fabrication without requiring separate masks for each threshold voltage type, thereby reducing manufacturing cost while maintaining precise threshold voltage differentiation.
Solution Approach 2:
The patent combines multiple implantation steps into a single implantation process by using a strategically designed mask that exposes different portions of different devices simultaneously. This merging of operations allows achieving different threshold voltages for multiple devices in one implantation step, eliminating the need for separate masks and reducing overall manufacturing complexity and cost.
3Manufacturing precision
If channel length is enlarged to accommodate higher threshold voltage devices, then threshold voltage is improved, but device space consumption increases and ON current decreases
Solution Approach 1:
The patent applies local quality by implementing selective implantation in specific portions of the channel rather than uniformly throughout the entire channel. This allows achieving the required threshold voltage adjustment in localized regions without needing to extend the overall channel length, thereby maintaining compact device geometry and preserving valuable IC device space while still achieving higher threshold voltage where needed.
4Manufacturing precision
If channel length is enlarged to accommodate higher threshold voltage devices, then threshold voltage is improved, but ON current and device operation speed decrease
Solution Approach 1:
The patent applies local quality by implementing selective implantation in specific portions of the channel rather than uniformly throughout the entire channel. This allows achieving the required threshold voltage adjustment in localized regions without needing to extend the overall channel length, thereby maintaining short channel lengths that support high ON current and fast device operation speed while still achieving higher threshold voltage where needed through localized doping modifications.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in improved ON current, reduced OFF current, and lower leakage currents, achieving better power efficiency and cost-effectiveness for integrated circuits, particularly beneficial for ultra-low power applications like the Internet of Things (IoT) market.
Implementation Method 1
channel and halo implantation optimization
Data Source
AI summary
The present disclosure provides an FET structure including a transistor of a first conductive type. The transistor includes a substrate having a region of a second conductive type, a channel between source and drain, and a gate over the channel. The channel includes dopants of the first conductive type. The gate includes a work function setting layer of the second conductive type. The present disclosure also provides a method for manufacturing an FET with multi-threshold voltages scheme. The method includes exposing channels of a first transistor of a first conductive type and a first transistor of a second conductive type from a first mask, doping the channels with dopants of the first conductive type, exposing channels of a second transistor of the first conductive type and a second conductive type from a second mask, and doping the channels with dopants of the second conductive type.