Multi-threshold Gate Structure with Doped Dielectric
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As semiconductor technology advances, there is a challenge in scaling down semiconductor devices like MOSFETs and finFETs to meet demands for higher storage capacity, faster processing, and lower costs, which increases power consumption and parasitic capacitance due to the difficulty in achieving multi-threshold voltages without consuming valuable IC device space or resulting in non-conformity from ion implantation shadow effects.
Innovation Solution
The use of multi-deposition and patterning processes to form doped gate dielectric layers with varying dopant concentrations and multi-layer metal work function materials in gate-all-around FETs, finFETs, and planar FETs, allowing for the creation of semiconductor devices with multiple threshold voltages by varying the crystallographic structure and spontaneous polarization through the formation of electric dipoles at interfaces between gate dielectric and work function layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If ion implantation is used to achieve multi-threshold voltages, then threshold voltage control is improved, but non-conformity occurs due to shadow effects and device space is consumed
Solution Approach 1:
The patent changes the physical and chemical parameters of the gate dielectric layer by doping it with different materials (e.g., tungsten, molybdenum, niobium, tantalum) at varying concentrations. This allows precise control of threshold voltage without ion implantation, eliminating shadow effects while achieving multi-threshold voltage functionality through compositional parameter variation
Solution Approach 2:
The patent employs composite gate dielectric structures combining multiple materials (e.g., hafnium oxide with tungsten, molybdenum, niobium, or tantalum dopants) to create distinct threshold voltage regions. These composite materials enable fine-tuned electrical properties and multi-threshold characteristics without the harmful shadow effects of ion implantation
2Productivity
If device dimensions are scaled down to increase storage capacity and processing speed, then storage capacity and processing speed are improved, but power consumption and parasitic capacitance increase
Solution Approach 1:
The patent applies local quality by creating spatially varying dopant concentrations within the gate dielectric layer. Different regions of the gate dielectric contain different amounts of dopant materials, enabling local control of electrical properties to optimize power consumption and reduce parasitic capacitance in specific device regions while maintaining high processing speed
Solution Approach 2:
By varying the compositional parameters of the gate dielectric (different dopant types and concentrations), the patent optimizes the electrical characteristics of scaled-down devices. This allows reduction of parasitic capacitance and power consumption through material composition control, enabling continued device scaling without proportionally increasing power consumption
3Quantity of substance
If device dimensions are scaled down to increase storage capacity, then storage capacity is improved, but parasitic capacitance increases
Solution Approach 1:
The patent utilizes parameter changes in the gate dielectric composition (varying dopant concentrations of tungsten, molybdenum, niobium, tantalum, etc.) to control and reduce parasitic capacitance. By adjusting these material parameters, the patent enables increased storage capacity through device scaling while simultaneously managing parasitic capacitance effects
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the optimization of delay and power consumption in semiconductor devices by achieving multiple threshold voltages without increasing device size, reducing parasitic capacitance, and improving functional density, thus addressing the limitations of existing scaling methods.
Implementation Method 1
varying the crystallographic structure and spontaneous polarization through the formation of electric dipoles at interfaces between gate dielectric and work function layers
Data Source
AI summary
The present disclosure describes a semiconductor device that includes a semiconductor device that includes a first transistor having a first gate structure. The first gate structure includes a first gate dielectric layer doped with a first dopant at a first dopant concentration and a first work function layer on the first gate dielectric layer. The first gate structure also includes a first gate electrode on the first work function layer. The semiconductor device also includes a second transistor having a second gate structure, where the second gate structure includes a second gate dielectric layer doped with a second dopant at a second dopant concentration lower than the first dopant concentration. The second gate structure also includes a second work function layer on the second gate dielectric layer and a second gate electrode on the second work function layer.