Multi-Threshold Gate Structure for Scaled GAA FETs
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Solution Overview
Problem
As semiconductor devices continue to scale down, there is a challenge in achieving multi-threshold voltages in GAA FETs due to space constraints and ion implantation non-conformity, leading to increased power consumption and parasitic capacitance.
Innovation Solution
The formation of multi-threshold voltage devices is achieved through the use of multi-layer metal work function layers and nitrogen incorporated work function layers, along with bi-layer hardmasks for etch selectivity, in GAA FETs, finFETs, and planar FETs, allowing for different threshold voltages without consuming valuable IC device space.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If semiconductor devices are scaled down to achieve higher storage capacity and faster processing, then storage capacity and processing speed are improved, but power consumption and parasitic capacitance increase
Solution Approach 1:
The patent applies different work function materials and thicknesses in different regions of the gate structure to create multi-threshold voltage zones. This allows different regions of the semiconductor device to operate at different threshold voltages, optimizing power consumption locally while maintaining high overall productivity through scaled dimensions.
Solution Approach 2:
The patent changes physical parameters by varying work function material composition and thickness to achieve different threshold voltages. This enables fine-tuning of device characteristics to balance power consumption against processing speed and storage capacity in scaled devices.
2Adaptability or versatility
If multi-threshold voltage devices are fabricated using conventional methods, then different threshold voltages are achieved, but ion implantation non-conformities and valuable IC device space are consumed
Solution Approach 1:
The patent segments the gate structure into multiple regions with different work function characteristics. This segmentation is achieved through selective deposition and etching processes that create distinct zones within the gate, enabling multi-threshold voltage operation without requiring separate device areas, thus conserving IC device space.
Solution Approach 2:
The patent transitions from planar multi-threshold implementation to a three-dimensional gate-all-around structure where different threshold voltages are achieved through vertical and radial variations in work function thickness. This dimensional change allows multiple threshold voltages to be packed into a smaller footprint area.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables efficient fabrication of semiconductor devices with varied threshold voltages, reducing power consumption and parasitic capacitance while optimizing functional density and geometry size.
Implementation Method 1
nitrogen incorporated work function layers, such as titanium aluminum carbon nitride
Implementation Method 2
multi-layer metal work function materials
Data Source
AI summary
The present disclosure describes a semiconductor device that includes a substrate and a first transistor on the substrate. The first transistor includes a first gate structure and the first gate structure includes a gate dielectric layer and a first work function layer on the gate dielectric layer. The first gate structure also includes a capping layer on the first work function layer. The semiconductor device also includes a second transistor on the substrate, in which the second transistor includes a second gate structure. The second gate structure includes the gate dielectric layer and a second work function layer on the gate dielectric layer. The second gate structure also includes the first work function layer on the second work function layer and the silicon capping layer on the first work function layer.