Multi-Threshold SOI Circuitry for Power-Speed Trade-off
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Solution Overview
Problem
Advanced integrated circuits face challenges in balancing device performance, power consumption, and circuit density, as improving one aspect often compromises another, such as increased power consumption due to low threshold voltage transistors for high-speed switching.
Innovation Solution
Implementing a method to apply bias voltages to buried wells in Silicon-on-Insulator (SOI) technology to create transistors with varying threshold voltages, allowing for the inclusion of both higher-threshold voltage transistors for low power consumption and lower-threshold voltage transistors for high-speed logic evaluation, using a combination of NFETs and PFETs that share wells under an insulator.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If low threshold voltage transistors are used for high-speed switching, then switching speed is improved, but power consumption increases
Solution Approach 1:
The patent applies different threshold voltages to different transistors within the same logic gate circuit. Specifically, header and footer transistors use high threshold voltages to minimize leakage current and power consumption, while internal transistors use low threshold voltages to enable fast switching. This local differentiation of transistor characteristics resolves the contradiction by optimizing each transistor's threshold voltage according to its specific functional role in the circuit.
Solution Approach 2:
The patent implements dynamic threshold voltage adjustment through body biasing techniques. By applying adjustable bias voltages to the substrate or well regions, the threshold voltage of transistors can be dynamically modified during operation. This allows the circuit to adapt threshold voltages based on operational requirements, achieving both high-speed switching and low power consumption at different times or under different conditions.
2Use of energy by moving object
If high threshold voltage transistors are used for low power consumption, then power consumption is reduced, but switching speed decreases
Solution Approach 1:
The patent strategically places high threshold voltage transistors (header and footer devices) only where needed for power consumption control, while maintaining low threshold voltage transistors for speed-critical paths. This localized application of high threshold voltage characteristics minimizes the impact on switching speed while achieving power reduction goals.
3Quantity of substance
If multiple threshold voltage transistors are integrated in the same well, then device density is improved, but well interference increases
Solution Approach 1:
The patent introduces isolation structures such as deep trenches filled with insulating material or additional buried oxide layers between adjacent wells containing transistors with different threshold voltages. These intermediary structures act as barriers that prevent electrical interference and threshold voltage modulation between neighboring wells, enabling high-density integration of multi-threshold voltage transistors without significant well interference.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables reduced power consumption while maintaining high switching speed, allowing for dynamic adjustment of threshold voltages to optimize performance and leakage current, thereby addressing the trade-offs in integrated circuit design.
Implementation Method 1
Voltage biasing is applied to the buried wells to impact the Vth of one or more transistors in logic gates
Data Source
AI summary
Multiple threshold voltage circuitry based on silicon-on-insulator (SOI) technology is disclosed which utilizes N-wells and/or P-wells underneath the insulator in SOI FETs. The well under a FET is biased to influence the threshold voltage of the FET. A PFET and an NFET share a common buried P-well or N-well. Various types of logic can be fabricated in silicon-on-insulator (SOI) technology using multiple threshold voltage FETs. Embodiments provide circuits including the advantageous properties of both low-leakage transistors and high-speed transistors.