Multi-tier Co-placement for 3D Integrated Circuitry
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Solution Overview
Problem
Conventional two-dimensional Electronic Design Automation (EDA) tools are inefficient for designing three-dimensional integrated circuits (3DICs) as they lack co-optimization between multiple tiers, leading to suboptimal placement of standard cells and inter-tier vias.
Innovation Solution
The implementation of a multi-tier co-placement method using an iterative bounding procedure and a placement director, which enables the clustering or grouping of standard cells and inter-tier vias across tiers, allowing for adaptable placement on an arbitrary grid structure, and utilizing both 2D and 3D placement engines for improved optimization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional 2D placement solution is used for 3DIC design, then the design process is simple, but the placement quality and optimization between multiple tiers is poor
Solution Approach 1:
The patent transitions from conventional 2D placement to 3D co-placement by introducing a vertical dimension (tiers) to the placement process. The placement director operates in 3D space to simultaneously determine positions of standard cells and inter-tier vias across multiple tiers, enabling true 3D optimization rather than sequential 2D placement.
Solution Approach 2:
The patent merges the placement of standard cells and inter-tier vias into a single co-optimization process. Instead of determining via locations separately after cell placement, the placement director simultaneously optimizes both elements together across multiple tiers, achieving integrated 3D placement quality.
2Manufacturing precision
If 2D placement solution is used, then the tool implementation is simple, but the co-optimization between multiple tiers is lacking
Solution Approach 1:
The patent introduces a placement director as an intermediary component that coordinates the co-placement process across multiple tiers. The placement director receives design inputs and outputs optimized placement configurations, mediating between the complex 3D optimization requirements and the actual placement execution.
Solution Approach 2:
The patent implements an iterative bounding procedure that dynamically adjusts placement constraints and parameters during the optimization process. The bounding boxes and placement parameters are refined through multiple iterations to converge on optimal 3D placement configurations.
Data Source
AI summary
Various implementations described herein are directed to a method that defines tiers of an integrated circuit having standard cells placed adjacent to each other in a multi-tier placement. The integrated circuit includes multi-tier nets connected with inter-tier connections. The method includes pairing inter-tier connections as inter-tier-connection pairs belonging to a same net. The method includes grouping standard cells in groups with or without inter-tier-connection pairs from the tiers. The method includes relating the standard cells with or without inter-tier-connection pairs within each group from the groups by generating a multi-tier fence boundary around physical locations of the standard cells with or without inter-tier-connection pairs. The method includes iteratively adjusting a location of the standard cells with or without a location of inter-tier connections so as to converge the location of the standard cells with or without the location of the inter-tier connections to optimized locations or legal locations.