Multi-Tier Interposer Package for Shorter Die-to-Die Routing
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Solution Overview
Problem
Existing semiconductor packages face challenges in achieving high signal integrity, power integrity, and overall performance due to limitations in conductive feature density and die-to-die routing distance.
Innovation Solution
The solution involves a semiconductor package design with multiple tiers of interposers, where bottom and top integrated circuit dies are bonded and electrically connected to interposers using dielectric-to-dielectric and metal-to-metal bonding, allowing for increased conductive feature density and reduced die-to-die routing distance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional single-tier packaging is used, then device structure is simple, but conductive feature density is limited and die-to-die routing distance is long
Solution Approach 1:
The package structure is segmented into multiple tiers with separate interposers for different functional blocks. Each interposer can be independently designed and optimized, allowing conductive features to be distributed across multiple levels rather than concentrated in a single plane. This segmentation enables higher effective conductive feature density while managing routing distances through localized connections within each tier.
Solution Approach 2:
The patent transitions from a two-dimensional single-tier layout to a three-dimensional multi-tier architecture. Conductive features are arranged across multiple vertical levels (z-dimension) in addition to horizontal planes (x-y dimensions). This dimensional expansion allows signals to route through multiple layers, effectively increasing the available conductive feature density and reducing routing distances by providing alternative vertical pathways.
2Reliability
If multi-tier interposer structure is implemented, then conductive feature density increases and die-to-die routing distance decreases, but manufacturing complexity increases
Solution Approach 1:
Die-to-interposer bonding is performed at an intermediate stage during wafer fabrication rather than as a final assembly step. This preliminary bonding allows subsequent processing steps to be performed on the entire wafer array simultaneously, including formation of through-silicon vias, metallization layers, and encapsulation. By performing bonding early, the patent avoids the complexity of handling and aligning individual bonded assemblies through multiple subsequent processing steps.
Solution Approach 2:
The patent combines multiple fabrication processes into integrated sequence operations. The bonding process is merged with wafer-level processing steps, allowing simultaneous fabrication of multiple dies and their interposer connections. Through-silicon via formation, metallization deposition, and encapsulation are combined into unified process flows that operate on the entire wafer array, reducing the number of discrete manufacturing steps and improving overall manufacturing efficiency.
3Reliability
If die-to-die routing distance is reduced, then signal integrity improves, but package density increases leading to manufacturing challenges
Solution Approach 1:
Interposers serve as intermediary substrates between adjacent dies, providing a common reference plane and alignment structure. The interposer's rigid substrate and predefined conductive feature patterns act as a mediator that simplifies the alignment process. Dies are bonded to the interposer using standard bonding techniques with well-established alignment tolerances, rather than requiring direct die-to-die alignment which would demand higher precision. The interposer absorbs and compensates for dimensional variations, enabling shorter routing distances without proportionally increasing alignment difficulty.
Data Source
AI summary
A semiconductor package with two interposers, and the method of forming the same are provided. The semiconductor package may include a first interposer, a first semiconductor die on the first interposer, a second interposer on the first semiconductor die, and a second semiconductor die on the second interposer. The second interposer may be between the first semiconductor die and the second semiconductor die. The first semiconductor die may be bonded to the first interposer by metal-to-metal bonding and dielectric-to-dielectric bonding. The second semiconductor die may be bonded to the second interposer by metal-to-metal bonding and dielectric-to-dielectric bonding.