Multi-Tier Memory Architecture for Disk Drive Caching

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Solution Overview

Problem

Non-volatile memory devices, such as solid-state memory, experience reliability degradation over time due to limited write cycles, leading to data corruption and errors, especially in multi-level cell (MLC) memory which has inferior endurance and retention compared to single-level cell (SLC) memory.

Innovation Solution

Implementing a multi-tier memory architecture that utilizes both SLC and MLC non-volatile memory tiers, with data stored in appropriate tiers based on characteristics like write frequency, read frequency, and retention duration, allowing for improved performance and cost-effectiveness by caching frequently accessed data in non-volatile memory.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If non-volatile memory is used for storing data, then reading and writing performance is improved, but reliability degrades over time due to limited write cycles

Engineering Contradiction:
Improvereading and writing performanceVSAvoiddata reliability over time
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The patent divides the non-volatile memory into multiple tiers (first tier with higher endurance, second tier with lower endurance) to segment the storage capacity. This allows different data types to be stored in different tiers based on their reliability requirements, resolving the contradiction between performance and reliability.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different memory tiers are assigned different quality characteristics (endurance, retention) based on local requirements. Critical data requiring high reliability is stored in the first tier, while less critical data is stored in the second tier, allowing each region to have the quality appropriate to its function.

Inventive Principle:
Principle #3Local quality

2Quantity of substance

If multi-level cell (MLC) memory is used, then storage capacity is increased, but endurance and retention are reduced

Engineering Contradiction:
Improvestorage capacityVSAvoidendurance and retention
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The memory is segmented into multiple tiers with different cell types (SLC and MLC). SLC memory provides high endurance for critical data, while MLC memory provides high capacity for less critical data, allowing the system to achieve both capacity and reliability.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent uses a composite memory architecture combining different types of non-volatile memory (SLC and MLC) in a unified tiered structure. This composite approach allows the system to leverage the complementary strengths of different memory technologies to achieve both capacity and reliability.

Inventive Principle:
Principle #40Composite materials

3Speed

If data is cached in non-volatile memory, then access performance is improved, but power consumption increases

Engineering Contradiction:
Improvedata access performanceVSAvoidpower consumption
Core Design Contradiction:
SpeedVSUse of energy by moving object

Solution Approach 1:

The cache is segmented into multiple tiers with different power consumption characteristics. By storing data in appropriate tiers based on access patterns, the system can optimize the balance between access performance and power consumption, reducing unnecessary power usage while maintaining fast access for frequently accessed data.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS8977803B2Disk drive data caching using a multi-tiered memory
Publication Date: 2015.03.10 WESTERN DIGITAL TECHNOLOGIES INC
  • US8977803B2 patent drawing
  • US8977803B2 patent drawing
  • US8977803B2 patent drawing

AI summary

A disk drive is disclosed that utilizes multi-tiered solid state memory for caching data received from a host. Data can be stored in a memory tier that can provide the required performance at a low cost. For example, multi-level cell (MLC) memory can be used to store data that is frequently read but infrequently written. As another example, single-level cell (SLC) memory can be used to store data that is frequently written. Improved performance, reduced costs, and improved power consumption can thereby be attained.