Multi-Tier 3D Memory Differential Etch Rate Field Oxides
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Solution Overview
Problem
In multi-tier three-dimensional memory devices, the increase in the number of electrically conductive layers poses challenges in forming contact via structures, leading to higher probabilities of electrical shorts and incomplete etch processes, which complicates the manufacturing process and increases costs.
Innovation Solution
The implementation of differential etch rate field oxides in different tier structures within a multi-tier memory device, where the first retro-stepped dielectric material portion has a higher etch rate than the second, allows for the formation of contact via structures in a single via etch process, reducing the likelihood of electrical shorts and opens.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If multiple via etch processes are used to form contact via structures through increasing numbers of electrically conductive layers, then the completeness of via formation is improved, but the manufacturing complexity and cost increase
Solution Approach 1:
The patent applies local quality by assigning different etch rate characteristics to different retro-stepped dielectric material portions. Specifically, the first retro-stepped dielectric material portion has a first etch rate while the second retro-stepped dielectric material portion has a second etch rate that is slower than the first. This localized differentiation allows a single via etch process to selectively progress through different dielectric layers at appropriate rates, enabling complete via formation through multiple conductive layers without requiring multiple separate etch processes.
2Reliability
If multiple via etch processes are used to ensure complete via formation, then the manufacturing reliability improves, but the probability of electrical shorts decreases only at the cost of increased processing steps
Solution Approach 1:
The patent employs parameter changes by modifying the etch rate parameter of different retro-stepped dielectric material portions. The first retro-stepped dielectric material portion is formulated with a first etch rate, while the second retro-stepped dielectric material portion is formulated with a second etch rate that is slower. This parameter differentiation enables a single via etch process to automatically adapt to the varying depths and material compositions encountered in multi-tier three-dimensional memory devices, ensuring reliable via formation through all electrically conductive layers while maintaining high manufacturing efficiency.
3Ease of manufacture
If a single via etch process is used to form contact via structures through multi-tier structures, then the manufacturing simplicity improves, but the etch rate uniformity across different dielectric layers becomes problematic
Solution Approach 1:
The patent resolves the etch rate uniformity problem by implementing local quality in the dielectric material formulation. Different retro-stepped dielectric material portions are composed with different etch rate characteristics - the first retro-stepped dielectric material portion has a first etch rate while the second retro-stepped dielectric material portion has a second etch rate that is slower. This localized material differentiation allows the single via etch process to maintain both simplicity and precision, as each dielectric layer etches at its appropriate rate to ensure complete via formation without requiring process adjustments.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach decreases the probability of electrical shorts and opens, simplifies the manufacturing process, and maintains the areal device density of three-dimensional memory devices by ensuring complete and accurate formation of contact via structures.
Implementation Method 1
forming contact via cavities through the first and second retro-stepped dielectric material portions using a reactive ion etch process that provides a higher average etch rate through the first retro-stepped dielectric material portion than through the second retro-stepped dielectric material portion
Data Source
AI summary
A three-dimensional memory device includes a first-tier structure containing a first alternating stack of first insulating layers and first electrically conductive layers that has first stepped surfaces, and a first retro-stepped dielectric material portion contacting the first stepped surfaces of the first alternating stack, and a second-tier structure containing a second alternating stack of second insulating layers and second electrically conductive layers that has second stepped surfaces, and a second retro-stepped dielectric material portion contacting the second stepped surfaces of the second alternating stack. The first retro-stepped dielectric material portion has a higher etch rate than the second retro-stepped dielectric material portion. Memory stack structures vertically extend through the first alternating stack and the second alternating stack. Each of the memory stack structures includes a memory film and a vertical semiconductor channel.