Multi-Tier Non-Volatile Memory Erase Bias for Uniform Speed
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Solution Overview
Problem
In non-volatile memory systems with multiple tiers, inner tiers erase at slower speeds than outer tiers, leading to reliability issues due to non-uniform erase speeds, which can result in programming errors and incorrect block marking.
Innovation Solution
Applying a larger voltage bias to the control gates of outer tiers than inner tiers during the erase process using a GIDL erase method to compensate for intrinsic erase speed differences, ensuring uniform erase speed across all tiers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a standard erase voltage is applied to all tiers during the erase process, then the outer tiers erase at high speed, but the inner tiers erase at slower speeds leading to non-uniform erase performance
Solution Approach 1:
The patent applies different voltage biases to control gates of memory cells in different tiers based on their specific erase speed characteristics. Outer tiers receive a first voltage bias while inner tiers receive a second voltage bias, creating localized quality adjustments that compensate for position-dependent erase speed variations and achieve uniform erase performance across all tiers
Solution Approach 2:
The patent changes the voltage bias parameter applied to control gates during the erase process. By adjusting the voltage bias level differently for inner tiers compared to outer tiers, the patent modifies the erase characteristics to compensate for the slower erase speed in inner tiers, thereby achieving uniform erase performance across all tiers
2Ease of manufacture
If the erase process does not compensate for tier position, then the process is simple, but programming errors and incorrect block marking occur due to non-uniform erase speeds
Solution Approach 1:
The patent implements localized quality control by applying different voltage biases to control gates in different tiers. This ensures that each tier receives the appropriate erase conditions for its specific characteristics, preventing programming errors and block marking issues while maintaining a relatively simple overall erase process structure
Solution Approach 2:
The patent incorporates feedback mechanisms to detect and respond to erase speed variations across different tiers. By monitoring erase progress and adjusting voltage biases accordingly, the system ensures reliable erase uniformity and prevents data integrity issues without requiring complex manual intervention
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach ensures consistent and reliable erasure across multiple tiers, preventing errors and maintaining device reliability by synchronizing erase speeds.
Implementation Method 1
Applying a larger voltage bias to the control gates of outer tiers than inner tiers during the erase process using a GIDL erase method to compensate for intrinsic erase speed differences
Data Source
AI summary
A non-volatile memory system comprises a plurality of non-volatile memory cells divided into three or more tiers. The memory cells can be programmed, erased and read. In order to achieve uniform erase speed for the three or more tiers, the erase process comprises applying a larger voltage bias to control gates of non-volatile memory cells in the outer tiers than the voltage bias applied to control gates of non-volatile memory cells in one or more inner tiers.